6,4 mm 55,0 mm
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
4.5-VTO20-VINPUT,6-AOUTPUTSYNCHRONOUSPWM
SWITCHERWITHINTEGRATEDFET(SWIFT™)
FEATURES
•••••••••••
40mΩMOSFETSwitchforHighEfficiencyat6-A(7.5Peak)OutputCurrentUsesExternalLowsideMOSFET
OutputVoltageAdjustableDownto0.891VWith1%Accuracy
SynchronizestoExternalClock180°OutofPhaseSynchronizationWidePWMFrequency–Fixed250kHz,500kHzorAdjustable250kHzto700kHzAdjustableSlowStart
AdjustableUndervoltageLockout
LoadProtectedbyPeakCurrentLimitandThermalShutdown
16-PinTSSOPPowerPAD™Package
SWIFTDocumentationApplicationNotes,andDesignSoftware:www.ti.com/swift
DESCRIPTION
TheTPS54550isamediumoutputcurrentsynchronousbuckPWMconverterwithanintegratedhighsideMOSFETandagatedriverforanlowsideexternalMOSFET.Featuresincludeahighperformancevoltageerroramplifierthatenablesmaximumperformanceundertransientconditionsandflexibilityinchoosingtheoutputfilterinductorsandcapacitors.TheTPS54550hasanunder-voltage-lockoutcircuittopreventstart-upuntiltheinputvoltagereaches4.5V;aslow-startcircuittolimitin-rushcurrents;andapowergoodoutputtoindicatevalidoutputconditions.Thesynchronizationfeatureisconfigurableaseitheraninputoranoutputforeasy180°outofphasesynchronization.
TheTPS54550deviceisavailableinathermallyenhanced16-pinTSSOP(PWP)PowerPAD™package.TIprovidesevaluationmodulesandtheSWIFT™Designersoftwaretooltoaidinquicklyachievinghigh-performancepowersupplydesignstomeetaggressiveequipmentdevelopmentcycles.
APPLICATIONS
••••
IndustrialandCommercialLowPowerSystems
LCDMonitorsandTVsComputerPeripherals
PointofLoadRegulationforHigh
PerformanceDSPs,FPGAs,ASICsandMicroprocessors
Simplified Schematic
TPS54550SYNCPWRGDSS/ENAVINInputVoltage1009590EFFICIENCY
vs
OUTPUT CURRENT
Efficiency - %VBIASCOMPBOOTPHLSG858075706560555001234IO- Output Current -A
56VI= 9 V,VO= 3.3 V,fsw= 700 kHzOutputVoltageVSENSEPGNDPWRPADPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
SWIFT,PowerPADaretrademarksofTexasInstruments.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
Copyright©2006,TexasInstrumentsIncorporated
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SLVS623A–MARCH2006–REVISEDAPRIL2006
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Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
ORDERINGINFORMATION
Tj
-40°Cto125°C
(1)(2)
OUTPUTVOLTAGEAdjustableto0.891V
PACKAGEPlasticHTSSOP(PWP)
PARTNUMBER(1)TPS54550PWP(2)
Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIwebsiteatwww.ti.com.
ThePWPpackageisalsoavailabletapedandreeled.AddanRsuffixtothedevicetype(i.e.,TPS54550PWPR).
PACKAGEDISSIPATIONRATINGS(1)
PACKAGE
16-PinPWPwithsolder(2)(1)(2)
THERMALIMPEDANCEJUNCTION-TO-AMBIENT
40.1°C/W
TA=25°CPOWERRATING
2.49
TA=70°CPOWERRATING
1.37
TA=85°CPOWERRATING
1.00
SeeFigure22forpowerdissipationcurves.TestBoardConditionsa.3inchx3inch
b.Thickness:0.062inchc.2PCBlayersd.2oz.Copper
e.SeeFigure26,Figure27andTPS54550evaluationmoduleuser'sguideforlayoutsuggestions.
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
ABSOLUTEMAXIMUMRATINGS
overoperatingfree-airtemperaturerangeunlessotherwisenoted(1)
UNIT
VINVSENSE
VI
Inputvoltagerange
UVLOSYNCSSENABOOTVBIASLSGSYNC
VO
Outputvoltagerange
RTPWRGDCOMPPHPH
IO
Sourcecurrent
LSG(SteadyStateCurrent)COMP,VBIASSYNC
LSG(SteadyStateCurrent)
IS
Sinkcurrent,
PH(SteadyStateCurrent)COMP
SSENA,PWRGD
Voltagedifferential
TJTstg(1)
JunctiontemperatureStoragetemperature
Leadtemperature1,6mm(1/16inch)fromcasefor10seconds
AGNDtoPGND
-0.3Vto21.5V-0.3Vto8.0V-0.3Vto8.0V-0.3Vto4.0V-0.3Vto4.0VVI(PH)+8.0V-0.3to8.5V-0.3to8.5V-0.3to4.0V-0.3to4.0V-0.3to6.0V-0.3to4.0V-1.5Vto22VInternallyLimited(A)
10mA3mA5mA100mA500mA3mA10mA±0.3V+150°C-65°Cto+150°C
260°C
Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
ELECTROSTATICDISCHARGE
MIN
HumanBodyModelChargedDeviceModel
HBMCDM
JESD22-A114JESD22-C101
TYP
MAX1.51.5
UNITkVkV
RECOMMENDEDOPERATINGCONDITIONS
MIN
VITJ
Inputvoltagerange
Operatingjunctiontemperature
4.5-40
NOM
MAX20125
UNITV°C
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ELECTRICALCHARACTERISTICS
TJ=-40°Cto125°C,VIN=4.5Vto20V(unlessotherwisenoted)
PARAMETER
SUPPLYCURRENTIQ
QuiescentcurrentStartthresholdvoltage
VIN
StopthresholdvoltageHysteresis
UNDERVOLTAGELOCKOUT(UVLOPIN)
Startthresholdvoltage
UVLO
StopthresholdvoltageHysteresis
BIASVOLTAGE(VBIASPIN)VBIAS
Outputvoltage
IVBIAS=1mA,VIN≥12VIVBIAS=1mA,VIN=4.5VTJ=25°C
7.54.40.8880.882
RTGroundedRTOpen
RT=100kΩ(1%resistortoAGND)
(1)
TESTCONDITIOINS
OperatingCurrent,PHpinopen,
NoexternallowsideMOSFET,RT=Hi-ZShutdown,SSENA=0V
MINTYPMAXUNIT
10.31.14.32
3.69
3.973501.20
1.02
1.101007.84.470.8910.8912505005002005180100360
2.5
0.6
0.8
2.38.04.50.8940.899300600575500101.244.49
mAmAVVmVVVmV
V
REFERENCESYSTEMACCURACY
Referencevoltage
OSCILLATOR(RTPIN)
InternallysetPWMswitchingfrequencyExternallysetPWMswitchingfrequencySYNCoutlow-to-highrisetime(10%/90%)
200400425
kHzkHznsns°nsnsVVVVkHzV/V
25%
180
VIN=4.5V
80%601.0
86%802.8
500
1.5
dBMHznAV/µsns
10%7708
-25%
VV
FALLINGEDGETRIGGEREDBIDIRECTIONALSYNCSYSTEM(SYNCPIN)
25pFtoground25pFtoground
DelayfromrisingedgetorisingedgeofPHpinsRT=100kΩRT=100kΩ
50kΩresistortoground,Nopullupresistor
SYNCouthigh-to-lowfalltime(90%/10%)(1)Fallingedgedelaytime(1)Minimuminputpulsewidth(1)
Delay(fallingedgeSYNCtorisingedgePH)(1)SYNCouthighlevelvoltageSYNCoutlowlevelvoltageSYNCinlowlevelthresholdSYNCinhighlevelthresholdSYNCinfrequencyrange(1)
FEED-FORWARDMODULATOR(INTERNALSIGNAL)
Modulatorgain
ModulatorgainvariationMinimumcontrollableONtime(1)Maximumdutyfactor(1)
ERRORAMPLIFIER(VSENSEandCOMPPINS)
Erroramplifieropenloopvoltagegain(1)Erroramplifierunitygainbandwidth(1)Inputbiascurrent,VSENSEpin
COMP
Outputvoltageslewrate(symmetric)(1)
VIN=12V,TJ=25°C
Percentageofprogrammedfrequency
-10%225
(1)4
Specifiedbydesign,notproductiontested.
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
ELECTRICALCHARACTERISTICS(continued)
TJ=-40°Cto125°C,VIN=4.5Vto20V(unlessotherwisenoted)
PARAMETER
SlowStart/ENABLE(SSENAPIN)
DisablelowlevelinputvoltageInternalslow-starttime(10%to90%)PullupcurrentsourcePulldownMOSFET
POWERGOOD(PWRGDPIN)
PowergoodthresholdRisingedgedelay(2)Outputsaturationvoltage
PWRGD
OutputsaturationvoltageOpendrainleakagecurrent
CURRENTLIMIT
Currentlimit
CurrentlimitHiccupTime(2)
THERMALSHUTDOWN
ThermalshutdowntrippointThermalshutdownhysteresis(2)
LOWSIDEMOSFETDRIVER(LSGPIN)
Turnonrisetime,(10%/90%)(2)Deadtime(2)
DriverONresistance
OUTPUTPOWERMOSFETS(PHPIN)
PhasenodevoltagewhendisabledVoltagedrop,lowsideFETanddiode
rDS(ON)(2)(3)
HighsidepowerMOSFETswitch(3)
DCconditionsandnoload,SSENA=0VVIN=4.5V,Idc=100mAVIN=12V,Idc=100mA
VIN=4.5V,BOOT-PH=4.5V,IO=0.5AVIN=12V,BOOT-PH=8V,IO=0.5A
0.51.131.086040
1.421.38
VVmΩ
VIN=4.5V,Capacitiveload=1000pFVIN=8V,Capacitiveload=1000pFVIN=12V
VIN=4.5Vsink/sourceVIN=12Vsink/source
1512607.55
nsnsΩ
1657
°C°C
VIN=12Vfs=500kHz
7.5
8.54.5
9.5
Ams
Risingvoltagefs=250kHzfs=500kHz
Isink=1mA,VIN>4.5VIsink=100µA,VIN=0VVoltageonPWRGD=6V
97%420.050.76
3
msVVµA
II(SSENA)=1mAfs=250kHz,RT=groundfs=500kHz,RT=Hi-Z(2)
1.8
(2)
TESTCONDITIOINSMINTYPMAX0.5
UNITVms
4.62.350.1
10
µAV
Specifiedbydesign,notproductiontested.ResistancefromVINtoPHpins.
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
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PINASSIGNMENTS
PWP PACKAGE(TOP VIEW)
VINVINUVLOPWRGD
RTSYNCSSENACOMP
NOTE:
12345678THERMALPAD(17)161514131211109BOOTPHPHLSGVBIASPGNDAGNDVSENSE
If there is not a Pin 1 indicator, turn device to enablereading the symbol from left to right. Pin 1 is at the lowerleft corner of the device.
TerminalFunctions
TERMINALNO.1,23456
NAMEVINUVLOPWRGDRTSYNC
DESCRIPTION
Inputsupplyvoltage,4.5Vto20V.MustbypasswithalowESR10-µFceramiccapacitor.
Undervoltagelockoutpin.ConnectinganexternalresistivevoltagedividerfromVINtothepinwilloverridetheinternaldefaultVINstartandstopthresholds.
Powergoodoutput.Opendrainoutput.Alowonthepinindicatesthattheoutputislessthanthedesiredoutputvoltage.ThereisaninternalrisingedgefilterontheoutputofthePWRGDcomparator.
Frequencysettingpin.ConnectaresistorfromRTtoAGNDtosettheswitchingfrequency.ConnectingtheRTpintogroundorfloatingwillsetthefrequencytoaninternallypreselectedfrequency.
BidirectionalsynchronizationI/Opin.SYNCpinisanoutputwhentheRTpinisfloatingorconnectedlow.TheoutputisafallingedgesignaloutofphasewiththerisingedgeofPH.SYNCmaybeusedasaninputto
synchronizetoasystemclockbyconnectingtoafallingedgesignalwhenanRTresistorisused.See180°OutofPhaseSynchronizationoperationintheApplicationInformationsection.
SlowStart/Enable.TheSSENApinisadualfunctionpinwhichprovidesalogicenable/disableandaslowstarttimeset.Below0.5V,thedevicestopsswitching.Floatpintoenable.Capacitortogroundadjuststheslowstarttime.SeeExtendingSlowStartTimesection.
Erroramplifieroutput.ConnectfrequencycompensationnetworkfromCOMPtoVSENSEpins.Invertingnodeerroramplifier.
Analogground—internallyconnectedtothesensitiveanaloggroundcircuitry.ConnecttoPGNDandPowerPAD.PowerGround—Noisyinternalground—ReturncurrentsfromtheLSGdriveroutputreturnthroughthePGNDpin.ConnecttoAGNDandPowerPAD.
Internal8.0Vbiasvoltage.A1.0µFceramicbypasscapacitanceisrequiredontheVBIASpin.GatedriveforlowsideMOSFET.Connectgateofn-channelMOSFET.Phasenode—ConnecttoexternalL-Cfilter.
Bootstrapforhighsidegatedriver.Connect24Ohmand0.1µFceramiccapacitorfromBOOTtoPHpins.PGNDandAGNDpinsmustbeconnectedtotheexposedpadforproperoperation.SeeFigure26foranexamplePCBlayout.
7SSENA
891011121314,151617
COMPVSENSEAGNDPGNDVBIASLSGPHBOOTPowerPAD
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
FUNCTIONALBLOCKDIAGRAM
BOOTVIN320 kΩUVLO125 kΩ1.2VUVLOHiccupOC Current LimitPH
SYNCRT2x OscillatorBias + DriveRegulatorPWM Ramp(Feed Forward)VBIASOCCOMPVSENSEVBIAS2ReferenceSystem5 µASS/ENAHiccupTimerHiccupErrorAmplifierPWMComparatorSQAdaptive DeadtimeandContol LogicVBIASLSG
RThermalShutdownPWRGD
UVLOVSENSE97% RefUVLORisingEdgeDelayTPS54550POWERPAD
VBIAS
PGND
AGND
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DETAILEDDESCRIPTION
UndervoltageLockout(UVLO)
Theundervoltagelockout(UVLO)systemhasaninternalvoltagedividerfromVINtoAGND.Thedefaultsforthestart/stopvaluesarelabeledVINandgiveninTable1.TheinternalUVLOthresholdcanbeoverriddenbyplacinganexternalresistordividerfromVINtoground.Theinternaldividervaluesareapproximately320kΩforthehighsideresistorand125kΩforthelowsideresistor.Thedividerratio(andthereforethedefaultstart/stopvalues)isquiteaccurate,buttheabsolutevaluesoftheinternalresistorsmayvaryasmuchas15%.IfhighaccuracyisrequiredforanexternallyadjustedUVLOthreshold,selectlowervalueexternalresistorstosettheUVLOthreshold.Usinga1-kΩresistorforthelowsideresistorR2(seeFigure1)isrecommended.UndernocircumstancesshouldtheUVLOpinbeconnecteddirectlytoVIN.
Table1.Start/StopVoltageThreshold
STARTVOLTAGETHRESHOLD
VIN(Default)
UVLO
4.491.24
STOPVOLTAGETHRESHOLD
3.691.02
SlowStartEnable(SSENA)andInternalSlowStart
OncetheSSENApinvoltageexceeds0.5V,theTPS54550startsoperation.TheTPS54550hasaninternaldigitalslowstartthatrampsthereferencevoltagetoitsfinalvaluein1150switchingcycles.Theinternalslowstarttime(10%-90%)isapproximatedbythefollowingexpression:T 1.15kSS_INTERNAL(ms)ƒs(kHz)(3)OncetheTPS54550deviceisinnormalregulation,
theSSENApinishigh.IftheSSENApinispulledbelowthestopthresholdof0.5V,switchingstopsandtheinternalslowstartresets.IfanapplicationrequirestheTPS54550tobedisabled,useopendrainoropencollectoroutputlogictointerfacetotheSSENApin(seeFigure2).TheSSENApinhasaninternalpullupcurrentsource.Donotuseexternalpullupresistors.
Input Voltage Supply
R1R21 kΩ320 kΩ125 kΩ5 µADisabledCSSEnabledFigure2.InterfacingtotheSSENAPin
Figure1.CircuitUsingExternalUVLOFunctionTheequationsforselectingtheUVLOresistorsare:
VIN(start) 1kp
R1)1kp
1.24V(1)(R1)1kp) 1.02V
VIN(stop)
1kp(2)Forapplicationswhichrequireanundervoltagelock
out(UVLO)thresholdgreaterthan4.49V,externalresistorsmaybeimplemented,seeFigure1,toadjustthestartvoltagethreshold.Forexample,anapplicationneedinganUVLOstartvoltageofapproximately7.8Vusingtheequation(1),R1iscalculatedtotheneareststandardresistorvalueof5.36kΩ.UsingEquation2,theinputvoltagestopthresholdiscalculatedas6.48V.
ExtendingSlowStartTime
Inapplicationsthatuselargevaluesofoutputcapacitancetheremaybeaneedtoextendtheslowstarttimetopreventthestartupcurrentfromtrippingthecurrentlimit.ThecurrentlimitcircuitisdesignedtodisablethehighsideMOSFETandresettheinternalvoltagereferenceforashortamountoftimewhenthehighsideMOSFETcurrentexceedsthecurrentlimitthreshold.Iftheoutputcapacitanceandloadcurrentcausethestartupcurrenttoexceedthecurrentlimitthreshold,thepowersupplyoutputwillnotreachthedesiredoutputvoltage.Toextendtheslowstarttimeandtoreducethestartupcurrent,anexternalcapacitorcanbeaddedtotheSSENApin.Theslowstartcapacitanceiscalculatedusingthefollowingequation:
CSS(µF)=5.55x10-3Tss(ms)
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
SwitchingFrequency(RT)
TheTPS54550hasaninternaloscillatorthatoperatesattwicethePWMswitchingfrequency.TheinternaloscillatorfrequencyiscontrolledbytheRTpin.GroundingtheRTpinsetsthePWMswitchingfrequencytoadefaultfrequencyof250kHz.FloatingtheRTpinsetsthePWMswitchingfrequencyto500kHz.
ConnectingaresistorfromRTtoAGNDsetsthefrequencyaccordingtoEquation4(seeFigure13).
RT(kp)
46000ƒ
s(kHz)–35.9
(4)
TheRTpincontrolstheSYNCpinfunctions.IftheRTpinisfloatingorgrounded,SYNCisanoutput.IftheswitchingfrequencyhasbeenprogrammedusingaresistorfromRTtoAGND,thenSYNCfunctionsasaninput.
Theinternalvoltagerampchargingcurrentincreaseslinearlywiththesetfrequencyandkeepsthefeedforwardmodulatorconstant(Km=8)regardlessofthefrequencysetpoint.
Table2.SwitchingFrequency,SYNCandRTPins
SWITCHINGFREQUENCY250kHz,internallyset500kHz,internallyset
Externallysetto250kHzto700kHzExternallysynchronizedfrequency
SYNCPIN
GeneratesSYNCoutputsignalGeneratesSYNCoutputsignalTerminatetoquietgroundwith10-kΩresistor.
SynchronizationSignal
RTPINAGNDFloat
R=215kΩto69kΩ
Use110kΩwhenRTfloatsand237kΩwhenRTisgroundedandusingthesyncoutsignalofanotherTPS54550.SetRTresistorequalto90%to110%ofexternalsynchronizationfrequency.
180°OutofPhaseSynchronization(SYNC)TheSYNCpinisconfigurableasaninputorasanoutput,perthedescriptionintheprevioussection.Whenoperatingasaninput,theSYNCpinisafalling-edgetriggeredsignal(seeFigure3andFigure4).Whenoperatingasanoutput,thesignal'sfallingedgeisapproximately180°outofphasewiththerisingedgeofthePHpins.Thus,twoTPS54550devicesoperatinginasystemcanshareaninputcapacitoranddrawripplecurrentattwicethefrequencyofasingleunit.
WhenoperatingthetwoTPS54550devices180°outofphase,thetotalRMSinputcurrentisreduced.Thusreducingtheamountofinputcapacitanceneededandincreasingefficiency.
WhensynchronizingaTPS54550toanexternalsignal,thetimingresistorontheRTpinmustbesetsothattheoscillatorisprogrammedtorunat90%to110%ofthesynchronizationfrequency.
NOTE:Donotusesynchronizationinputfordesignswithoutputvoltages>10V.
VI(SYNC)
VO(PH)
Figure3.SYNCInputWaveform
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Internal Oscillator
VO(PH)
VO(SYNC)
Figure4.SYNCOutputWaveform
PowerGood(PWRGD)
TheVSENSEpiniscomparedtoaninternalreferencesignal,iftheVSENSEisgreaterthan97%andnootherfaultsarepresent,thePWRGDpinpresentsahighimpedance.AlowonthePWRGDpinindicatesafault.ThePWRGDpinhasbeendesignedtoprovideaweakpull-downandindicatesafaultevenwhenthedeviceisunpowered.IftheTPS54550haspowerandhasanyfaultflagset,theTPS54550indicatesthepowerisnotgoodbydrivingthePWRGDpinlow.Thefollowingevents,singlyorincombination,indicatepowerisnotgood:•VSENSEpinoutofbounds•Overcurrent
•Thermalshutdown•UVLOundervoltage
•Inputvoltagenotpresent(weakpull-down)•Slow-starting
•VBIASvoltageislow
OncethePWRGDpinpresentsahighimpedance(i.e.,powerisgood),aVSENSEpinoutofboundsconditionforcesPWRGDpinlow(i.e.,powerisbad)afteratimedelay.ThistimedelayisafunctionoftheswitchingfrequencyandiscalculatedusingEquation5:T 1000msdelayƒ
s(kHz)(5)
Upto1mAofcurrentcanbedrawnforuseinan
externalapplicationcircuit.TheVBIASpinmusthaveabypasscapacitorvalueof1.0µF.X7RorX5Rgradedielectricceramiccapacitorsarerecommendedbecauseoftheirstablecharacteristicsovertemperature.
BootstrapVoltage(BOOT)
TheBOOTcapacitorobtainsitschargecyclebycyclefromtheVBIAScapacitor.AcapacitorandsmallvalueresistorfromtheBOOTpintothePHpinsisrequiredforoperation.Thebootstrapconnectionforthehighsidedrivermusthaveabypasscapacitorof0.1µFandresistor24Ohm.
ErrorAmplifier
TheVSENSEpinistheerroramplifierinvertinginput.Theerroramplifierisatruevoltageamplifierwith1.5mAofdrivecapabilitywithaminimumof60dBofopenloopvoltagegainandaunitygainbandwidthof2MHz.
VoltageReference
Thevoltagereferencesystemproducesaprecisionreferencesignalbyscalingtheoutputofatemperaturestablebandgapcircuit.Duringproductiontesting,thebandgapandscalingcircuitsaretrimmedtoproduce0.891Vattheoutputoftheerroramplifier,withtheamplifierconnectedasavoltagefollower.Thetrimprocedureimprovestheregulation,sinceitcancelsoffseterrorsinthescalinganderroramplifiercircuits.
BiasVoltage(VBIAS)
TheVBIASregulatorprovidesastablesupplyfortheinternalanalogcircuitsandthelowsidegatedriver.
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
PWMControlandFeedForward
Signalsfromtheerroramplifieroutput,oscillator,andcurrentlimitcircuitareprocessedbythePWMcontrollogic.Referringtotheinternalblockdiagram,thecontrollogicincludesthePWMcomparator,PWMlatch,andtheadaptivedead-timecontrollogic.Duringsteady-stateoperationbelowthecurrentlimitthreshold,thePWMcomparatoroutputandoscillatorpulsetrainalternatelyresetandsetthePWMlatch.OncethePWMlatchisreset,thelow-sidedriverandintegratedpull-downMOSFETremainonforaminimumdurationsetbytheoscillatorpulsewidth.Duringthisperiod,thePWMrampdischargesrapidlytothevalleyvoltage.Whentherampbeginstochargebackup,thelow-sidedriverturnsoffandthehigh-sideFETturnson.ThepeakPWMrampvoltagevariesinverselywithinputvoltagetomaintainaconstantmodulatorandpowerstagegainof8V/V.AsthePWMrampvoltageexceedstheerroramplifieroutputvoltage,thePWMcomparatorresetsthelatch,thusturningoffthehigh-sideFETandturningonthelow-sideFET.Thelow-sidedriverremainsonuntilthenextoscillatorpulsedischargesthePWMramp.Duringtransientconditions,theerroramplifieroutputcanbebelowthePWMrampvalleyvoltageorabovethePWMpeakvoltage.Iftheerroramplifierishigh,thePWMlatchisneverresetandthehigh-sideFETremainsonuntiltheoscillatorpulsesignalsthecontrollogictoturnthehigh-sideFEToffandtheinternallow-sideFETanddriveron.Thedeviceoperatesatitsmaximumdutycycleuntiltheoutputvoltagerisestotheregulationsetpoint,settingVSENSEtoapproximatelythesamevoltageastheinternalvoltagereference.Iftheerroramplifieroutputislow,thePWMlatchiscontinuallyresetandthehigh-sideFETdoesnotturnon.Theinternallow-sideFETandlowsidedriverremainonuntiltheVSENSEvoltagedecreasestoarangethatallowsthePWMcomparatortochangestates.TheTPS54550iscapableofsinkingcurrentthroughtheexternallowsideFETuntiltheoutputvoltagereachestheregulationsetpoint.
Theminimumontimeisdesignedtobe180ns.Duringtheinternalslow-startinterval,theinternal
referencerampsfrom0Vto0.891V.Duringtheinitialslow-startinterval,theinternalreferencevoltageisverysmallresultinginacoupleofskippedpulsesbecausetheminimumontimecausestheactualoutputvoltagetobeslightlygreaterthanthepresetoutputvoltageuntiltheinternalreferencerampsup.
DeadtimeControl
Adaptivedeadtimecontrolpreventsshootthroughcurrentfromflowingintheintegratedhigh-sideMOSFETandtheexternallow-sideMOSFETduringtheswitchingtransitionsbyactivelycontrollingtheturnontimesofthedrivers.Thehigh-sidedriverdoesnotturnonuntilthevoltageatthegateofthelow-sideMOSFETisbelow1V.Thelow-sidedriverdoesnotturnonuntilthevoltageatthegateofthehigh-sideMOSFETisbelow1V.
LowSideGateDriver(LSG)
LSGistheoutputofthelow-sidegatedriver.The100-mAMOSFETdriveriscapableofprovidinggatedriveformostpopularMOSFETssuitableforthisapplication.UsetheSWIFTDesignerSoftwareTooltofindthemostappropriateMOSFETfortheapplication.ConnecttheLSGpindirectlytothegateofthelow-sideMOSFET.Donotuseagateresistorastheresultingturn-ontimemaybetooslow.
ThermalShutdown
ThedeviceusesthethermalshutdowntoturnofftheMOSFETdriversandcontrollerifthejunctiontemperatureexceeds165°C.Thedeviceisrestartedautomaticallywhenthejunctiontemperaturedecreasesto7°Cbelowthethermalshutdowntrippointandstartsupundercontroloftheslow-startcircuit.
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OvercurrentProtection
Overcurrentprotectionisimplementedbysensingthedrain-to-sourcevoltageacrossthehigh-sideMOSFETandcomparedtoavoltagelevelwhichrepresentstheovercurrentthresholdlimit.Ifthedrain-to-sourcevoltageexceedstheovercurrentthresholdlimitformorethan100ns,thehigh-sideMOSFETisdisable,theSSENApinispulledlow,andtheinternaldigitalslow-startisresetto0V.SSENAisheldlowforapproximatelythetimethatiscalculatedbyEquation6:T 2250HICCUP(ms)ƒs(kHz)(6)Oncethehiccuptimeiscomplete,theSSENApinis
releasedandtheconverterinitiatestheinternalslow-start.
OUTPUTVOLTAGE(V)
1.21.51.82.53.3
R2VALUE(kΩ)
28.714.79.765.493.74
OutputVoltageLimitations
DuetotheinternaldesignoftheTPS54550therearebothupperandloweroutputvoltagelimitsforanygiveninputvoltage.Additionally,thelowerboundaryoftheoutputvoltagesetpointrangeisalsodependentonoperatingfrequency.TheupperlimitoftheoutputvoltagesetpointisconstrainedbythemaximumdutycycleofthedeviceandisshowninFigure12.Thelowerlimitisconstrainedbytheminimumcontrollableontimewhichmaybeashighas220ns.TheapproximateminimumoutputvoltageforagiveninputvoltageandrangeofoperatingfrequenciesisshowninFigure8whilethemaximumoperatingfrequencyversusinputvoltageforsomecommonoutputvoltagesisshowninFigure10.Thecurvesshowninthesetwofiguresarevalidforoutputcurrentsgreaterthan0.5A.Asoutputcurrentsdecreasetowardsnoload(0A),theminimumoutputvoltagedecreases.Forapplicationswheretheloadcurrentislessthan100mA,thecurvesshowninFigure9andFigure11areapplicable.Allofthedataplottedinthesecurvesareapproximateandtakeintoaccountapossible20percentdeviationinactualoperatingfrequencyrelativetotheintendedsetpoint.
SettingtheOutputVoltage
TheoutputvoltageoftheTPS54550canbesetbyfeedingbackaportionoftheoutputtotheVSENSEpinusingaresistordividernetwork.IntheapplicationcircuitofFigure29,thisdividernetworkiscomprisedofresistorsR1andR2.Tocalculatetheresistorvaluestogeneratetherequiredoutputvoltageusethefollowingequation:R2R1 0.891
VO)0.891(7)StartwithafixedvalueofR1andcalculatethe
requiredR2value.Assumingafixedvalueof10kΩforR1,thefollowingtablegivestheappropriateR2valueforseveralcommonoutputvoltages:
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TYPICALCHARACTERISTICS
ONRESISTANCE
vs
JUNCTIONTEMPERATURE
908070
VIN= 4.5 V8.258.50TJ= 25°CCURRENTLIMIT
vs
INPUTVOLTAGE
Vref − Internal Voltage Reference − VINTERNALVOLTAGEREFERENCE
vs
JUNCTIONTEMPERATURE
0.8912
VIN = 12 V0.89100.89080.89060.89040.89020.8900
0.8898
−50−25
On Resistance - mW50403020100-50-250255075100125150TJ- Junction Temperature - °C
VIN= 12 VCurrent Limit -A60
87.757.5005101520VI- Input Voltage - V
250255075100125150
TJ − Junction Temperature − 5C
Figure5.
MINIMUMOUTPUTVOLTAGE
vs
INPUTVOLTAGE
5.55Minimum Output Voltage − V4.5Minimum Output Voltage − V43.532.521.510.50300 kHz200 kHz400 kHz600 kHz500 kHz700 kHzIO > 0.5 A5.554.543.532.521.510.50Figure6.
MINIMUMOUTPUTVOLTAGE
vs
INPUTVOLTAGE
Maximum Switching Frequency − kHzIO = 0 A700 kHz600 kHz500 kHz400 kHz300 kHzFigure7.
MAXIMUMSWITCHINGFREQUENCY
vs
INPUTVOLTAGE
800700600500400300200100
0VO = 1.8 VVO = 1.5 VVO = 0.9 VVO = 1.2 VIO > 0.5 A567891011121314151617181920VI − Input Voltage − V
VO = 2.5 VVO = 3.3 V200 kHz567891011121314151617181920VI − Input Voltage − V
567891011121314151617181920VI − Input Voltage − V
Figure8.
MAXIMUMSWITCHINGFREQUENCY
vs
INPUTVOLTAGE
800Maximum Switching Frequency − kHz700VO = 3.3 VVO− Output Voltage − V600500400300200100IO < 0.1 A0567891011121314151617181920VI − Input Voltage − V
VO = 0.9 VVO = 1.8 V14
VO = 2.5 V12
Figure9.
MAXIMUMOUTPUTVOLTAGE
vs
INPUTVOLTAGE
225200RT Resistance − kW1751501251007550200
Figure10.
RTRESISTANCE
vs
SWITCHINGFREQUENCY
10864200
5
10
15
20
25
VI− Input Voltage − V
VO = 1.2 VVO = 1.5 V300400500600700
Switching Frequency − kHz
Figure11.Figure12.Figure13.
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TYPICALCHARACTERISTICS(continued)
VIN(UVLO)STARTANDSTOP
vs
FREE-AIRTEMPERATURE
4.5
TJ = 25°C10ENABLEDSUPPLYCURRENT
vs
INPUTVOLTAGE
1.3
DISABLEDSUPPLYCURRENT
vs
INPUTVOLTAGE
TJ = 25°C4.3
Start4.1
8SwitchingDisabled Supply Current − mA25ICC- Supply Current - mAVI − Input Voltage − V1.2
61.1
3.9
Stop4Non Switching3.7
1.0
23.5
−50−25
00.9
05101520VI- Input Voltage - V
02550751001251500510152025
TA − Free-Air Temperature − 5CVI − Input Voltage − V
Figure14.BIASVOLTAGE
vs
INPUTVOLTAGE
8.0
PWRGD − Power Good Threshold − %7.5VBIAS − Bias Voltage − V7.06.56.05.55.04.54.0
0
5
10
15
20
25
VI − Input Voltage − V
TJ = 25°C98.0
Figure15.
POWERGOODTHRESHOLD
vs
JUNCTIONTEMPERATURE
4.54
97.5
Power Good Delay − ms3.532.521.510.5
96.0
−50−25
0
0
25
50
75
100125150
250
350
Figure16.
POWERGOODDELAY
vs
SWITCHINGFREQUENCY
97.0
96.5
450550650750
TJ − Junction Temperature − 5C
Switching Frequency − kHz
Figure17.PHVOLTAGE
vs
PHSINKCURRENT
20.500.45
Figure18.
SLOWSTARTCAPACITANCE
vsTIME
54.5Slow Start Time − ms43.532.521.51250
350
Figure19.
INTERNALSLOWSTARTTIME
vs
SWITCHINGFREQUENCY
Slow Start Capacitance−mF1.75PH Voltage − V0.400.350.300.250.200.150.100.05
VI = 4.5 V1.50VI = 12 V1.251100150200250300ICC− Supply Current − mA
0
01020304050607080450550650750
t−Time−ms
Switching Frequency − kHz
Figure20.Figure21.Figure22.
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TYPICALCHARACTERISTICS(continued)
HICCUPTIME
vs
SWITCHINGFREQUENCY
10
TA- Free-Air Temperature - °C125FREE-AIRTEMPERATURE
vs
MAXIMUMOUTPUTCURRENT
32.5
POWERDISSIPATION
vs
FREE-AIRTEMPERATURE
98
Hiccup Time − ms765432250
PD- Power Dissipation - W10021.5
75501
qJA= 40.1°C/W
0.5025
5075100TA- Free-Air Temperature - °C
125
25VI= 12 V,VO= 3.3 V012345IO- Output Current -A
670350450550650750
Switching Frequency − kHz
Figure23.Figure24.Figure25.
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APPLICATIONINFORMATION
VinINPUTBYPASSCAPACITORUNDER VOLTAGELOCK OUTRESISTOR DIVIDERINPUTBULKFILTERTOPSIDE GROUNDAREALOWSIDEFETVOUTPHOUTPUTINDUCTOROUTPUTFILTERCAPACITORBOOTCAPACITORANDRESISTORVINVINUVLOBOOTPHPHLSGBIASCAPACITOR3.3 OR 5 VPWRGDPOWER GOOD PULLUPRTEXPOSEDPOWERPADAREAVBIASFREQUENCYSETRESISTORTERMINATION RES. (10 K)SYNCSS/ENAPGNDAGNDVSENSECOMPSLOW STARTCAPACITORCOMPENSATION NETWORKANALOG GROUNDTRACEVIA
BACKSIDE or INTERNALLAYERTRACE
Figure26.TPS54550PCBLayout
PCBLAYOUT
TheVINpinsshouldbeconnectedtogetherontheprintedcircuitboard(PCB)andbypassedwithalowESRceramicbypasscapacitor.Careshouldbetakentominimizetheloopareaformedbythebypasscapacitorconnections,theVINpins,andsourceofthelowsideMOSFET.Theminimumrecommendedbypasscapacitanceis10-µFceramicwithaX5RorX7RdielectricandtheoptimumplacementisclosesttotheVINpinsandthesourceofthelowsideMOSFET.SeeFigure26foranexampleofaboardlayout.TheAGNDandPGNDpinsshouldbetiedtothePCBgroundplaneatthepinsoftheIC.Thesourceofthelow-sideMOSFETshouldbeconnecteddirectlytothePCBgroundplane.ThePHpinsshouldbetiedtogetherandroutedtothedrainofthelow-sideMOSFET.SincethePHconnectionistheswitchingnode,theMOSFETshouldbelocatedveryclosetothePHpins,andtheareaofthePCB
conductorminimizedtopreventexcessivecapacitivecoupling.Therecommendedconductorwidthfrompins14and15is0.050inchto0.075inchof1-ounceto2-ouncecopper.Thelengthofthecopperlandpatternshouldbenomorethan0.2inch.
Foroperationatfullratedload,theanaloggroundplanemustprovideadequateheatdissipatingarea.A3-inchby3-inchplaneofcopperisrecommended,thoughnotmandatory,dependentonambienttemperatureandairflow.Mostapplicationshavelargerareasofinternalgroundplaneavailable,andthePowerPADshouldbeconnectedtothelargestareaavailable.Additionalareasonthebottomortoplayersalsohelpdissipateheat,andanyareaavailableshouldbeusedwhen5Aorgreateroperationisdesired.ConnectionfromtheexposedareaofthePowerPADtotheanaloggroundplanelayershouldbemadeusing0.013-inchdiameterviastoavoidsolderwickingthroughthevias.FourviasshouldbeinthePowerPADareawithfouradditionalviasoutsidethepadareaandunderneaththepackage.Additionalviasbeyondthoserecommendedtoenhancethermalperformanceshouldbeincludedinareasnotunderthedevicepackage.
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Minimum recommended thermal vias: 4 x 0.013 dia. Insideexposed PowerPAD area and 4 x 0.013 dia. Under device as
shown.Additional vias may be used if top side ground area is extended.
0.013 DIA8 PL0.1970.0500.0400.120Minimum recommended topsideAnalog Ground area.0.2300.1340.080Connect Pin 10AGND and Pin 11 PGNDtoAnalog Ground plane in this area foroptimum performance.Figure27.ThermalConsiderationsforPowerPADLayout
MODELFORLOOPRESPONSE
TheFigure28showsanequivalentmodelfortheTPS54550controlloopwhichcanbemodeledinacircuitsimulationprogramtocheckfrequencyresponseanddynamicloadresponse.TheerroramplifierintheTPS54550isavoltageamplifierwith80dB(10000V/V)ofopenloopgain.Theerroramplifiercanbemodeledusinganidealvoltage-controlledcurrentsourceasshowninFigure28witharesistorandcapacitorontheoutput.TheTPS54550devicehasanintegratedfeedforwardcompensationcircuitwhicheliminatestheimpactoftheinputvoltagechangestotheoveralllooptransferfunction.
Thefeedforwardgainismodeledasanidealvoltage-controlledvoltagesourcewithagainof8V/V.The1-mVacvoltagebetweennodesaandbeffectivelybreaksthecontrolloopforthefrequencyresponsemeasurements.Plottingb/cshowsthesmall-signalresponseofthepowerstage.Plottingc/ashowsthesmall-signalresponseofthefrequencycompensation.Plottinga/bshowsthesmall-signalresponseoftheoverallloop.ThedynamicloadresponsecanbecheckedbyreplacingtheRLwithacurrentsourcewiththeappropriateloadstepamplitudeandsteprateinatimedomainanalysis.
0.02560.0500.0400.015 x 16Minimum recommended exposed copperarea for PowerPAD. Some stencils mayrequire 10 percent larger area.SubmitDocumentationFeedback
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RdcPHLO1 mVESRCOaR(switch)+10 MΩ–+–40 mΩTPS545508 V/VbR1R5C8VSENSERL
+–20 V/V+10 MΩ–50 pF–10 MΩ+50 µA/V0.891REFR2R3C7C6cCOMPFigure28.ModelofControlLoop
+Figure29.ApplicationCircuit,3.3VOutput
Figure29showstheschematicforatypicalTPS54550application.TheTPS54550canprovideupto5-Aoutputcurrentatanominaloutputvoltageof3.3V.Forproperthermalperformance,theexposedPowerPADunderneaththedevicemustbesoldereddowntotheprintedcircuitboard.
DESIGNPROCEDURE
ThefollowingdesignprocedurecanbeusedtoselectcomponentvaluesfortheTPS54550.Alternately,theSWIFTDesignerSoftwaremaybeusedtogenerateacompletedesign.TheSWIFTDesignerSoftwareusesaniterativedesignprocedureandaccessesacomprehensivedatabaseofcomponentswhengeneratingadesign.Thissectionpresentsasimplifieddiscussionofthedesignprocess.
Tobeginthedesignprocessafewparametersmustbedecidedupon.Thedesignerneedstoknowthefollowing:
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pVIN
IOUT(MAX) 0.25CBULK ƒsw
)IOUT(MAX) ESRMAX
••••••InputvoltagerangeOutputvoltageInputripplevoltageOutputripplevoltageOutputcurrentratingOperatingfrequency
ǒǓ
(9)
WhereIOUT(MAX)isthemaximumloadcurrent,fSWistheswitchingfrequency,CBULKisthebulkcapacitorvalueandESRMAXisthemaximumseriesresistanceofthebulkcapacitor.
ThemaximumRMSripplecurrentalsoneedstobechecked.Forworstcaseconditions,thiscanbeapproximatedbyEquation10:
I
OUT(MAX)
I CIN2(10)Inthiscasetheinputripplevoltagewouldbe140mVandtheRMSripplecurrentwouldbe2.5A.Itisalsoimportanttonotethattheactualinputvoltageripplewillbegreatlyaffectedbyparasiticsassociatedwiththelayoutandtheoutputimpedanceofthevoltagesource.TheactualinputvoltagerippleforthiscircuitisshowninFigure34andislargerthanthecalculatedvalue.Thismeasuredvalueisstillbelowthespecifiedinputlimitof300mV.ThemaximumvoltageacrosstheinputcapacitorswouldbeVINmaxplusdeltaVIN/2.Thechosenbulkandbypasscapacitorsareeachratedfor25Vandthecombinedripplecurrentcapacityisgreaterthan3A,bothprovidingamplemargin.Itisveryimportantthatthemaximumratingsforvoltageandcurrentarenotexceededunderanycircumstance.
Forthisdesignexample,usethefollowingastheinputparameters:
DESIGNPARAMETERInputvoltagerangeOutputvoltageInputripplevoltageOutputripplevoltageOutputcurrentratingOperatingfrequency
EXAMPLEVALUE
6Vto17V3.3V300mV30mV5A700kHz
NOTE:Asanadditionalconstraint,thedesignissetuptobesmallsizeandlowcomponentheight.
SWITCHINGFREQUENCY
TheswitchingfrequencyissetusingtheRTpin.GroundingtheRTpinsetsthePWMswitchingfrequencytoadefaultfrequencyof250kHz.FloatingtheRTpinsetsthePWMswitchingfrequencyto500kHz.ByconnectingaresistorfromRTtoAGND,anyfrequencyintherangeof250to700kHzcanbeset.UseEquation8todeterminethepropervalueofRT.
46000RT(kp))
ƒs(kHz) 35.9(8)Inthisexamplecircuit,thedesired
frequencyis700kHzandRTis69.8kΩ.
switching
OUTPUTFILTERCOMPONENTS
Twocomponentsneedtobeselectedfortheoutputfilter,L1andC2.SincetheTPS54550isanexternallycompensateddevice,awiderangeoffiltercomponenttypesandvaluescanbesupported.InductorSelection
Tocalculatetheminimumvalueoftheoutputinductor,useEquation11:
V)V
OUT(MAX)IN(MAX)OUT
LMINV K I F
IN(max)INDOUTSW
V
INPUTCAPACITORS
TheTPS54550requiresaninputdecoupling
capacitorand,dependingontheapplication,abulkinputcapacitor.Theminimumrecommendedvalueforthedecouplingcapacitor,C9,is10µF.AhighqualityceramictypeX5RorX7Risrecommended.Thevoltageratingshouldbegreaterthanthemaximuminputvoltage.Asmallervaluemaybeusedsolongasallotherrequirementsaremet,however10µFhasbeenshowntoworkwellinawidevarietyofcircuits.Additionallysomebulkcapacitancemaybeneeded,especiallyiftheTPS54550circuitisnotlocatedwithinabout2inchesfromtheinputvoltagesource.Thevalueforthiscapacitorisnotcriticalbutshouldberatedtohandlethemaximuminputvoltageincludingripplevoltageandshouldfiltertheoutputsothatinputripplevoltageisacceptable.
ThisinputripplevoltagecanbeapproximatedbyEquation9:
ǒǓ
(11)
KINDisacoefficientthatrepresentstheamountofinductorripplecurrentrelativetothemaximumoutputcurrent.Igeneralthisvalueisatthediscretionofthedesigner,howeverthefollowingguidelinesmaybeused.FordesignsusinglowESRoutputcapacitorssuchasceramics,avalueashighasKIND=0.3maybeused.WhenusinghigherESRoutputcapacitors,KIND=0.2yieldsbetterresults.
ForthisdesignexampleuseKIND=0.3andtheminimuminductorvalueiscalculatedtobe3µH.Forthisdesignalargevaluewaschosen,6.8µH.
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FortheoutputfilterinductoritisimportantthattheRMScurrentandsaturationcurrentratingsnotbeexceeded.TheRMSinductorcurrentcanbefoundfromEquation12:
I
ǒ
L(RMS)
ȡ1
I2) OUT(MAX)12ǓV
VIN(MAX)VOUTOUT
LOUT
FSW
Ǔ
VIN(MAX)
0.82
(12)
39µF.Inthisdesignamoreconsevativefrequency
multiplierof3isusedresultinginadesiredoutputcapacitanceof200µF.Theselectedoutputcapacitormustberatedforavoltagegreaterthanthedesiredoutputvoltageplusonehalftheripplevoltage.Anyderatingamountmustalsobeincluded.ThemaximumRMSripplecurrentintheoutputcapacitorisgivenbyEquation15:
VOUT VIN(MAX))VOUT
1ICOUT(RMS) 12V L F N
IN(MAX)OUTSWC
andthepeakinductorcurrentcanbedeterminedwith
Equation13:
V
IL(PK)ǒI
OUT(MAX)
)
OUT
VIN(MAX)V
OUT
OUT
FǓ
(13)
ȡȧȢ
ǒ
Ǔȣ
ȧȤ
(15)
1.6 VIN(MAX) LSW
Forthisdesign,theRMSinductorcurrentis5.04Aandthepeakinductorcurrentis5.35A.ThechoseninductorisaSumidaCDRH105-6R86.8µH.Ithasasaturationcurrentratingof5.4AandaRMScurrentratingof5.4A,meetingtheserequirements.Asmallervalueinductorcouldbeused,howeverthisvaluewaschosenbecauseithasthelargestvalueinthisstylethatmetthecurrentratingrequirements.Largervalueinductorswillhaveloweraccurrentandresultinloweroutputvoltageripple.Ingeneral,inductorvaluesforusewiththeTPS54550areintherangeof6.8µHto47µH.CapacitorSelection
Theimportantdesignfactorsfortheoutputcapacitoraredcvoltagerating,ripplecurrentrating,andequivalentseriesresistance(ESR).Thedcvoltageandripplecurrentratingscannotbeexceeded.TheESRisimportantbecausealongwiththeinductorcurrentitdeterminestheamountofoutputripplevoltage.Theactualvalueoftheoutputcapacitorisnotcritical,butsomepracticallimitsdoexist.ConsidertherelationshipbetweenthedesiredclosedloopcrossoverfrequencyofthedesignandLCcornerfrequencyoftheoutputfilter.Ingeneral,itisdesirabletokeeptheclosedloopcrossoverfrequencyatlessthan1/5oftheswitchingfrequency.Withhighswitchingfrequenciessuchasthe700-kHzfrequencyofthisdesign,internalcircuitlimitationsoftheTPS54550limitthepracticalmaximumcrossoverfrequencytoabout50kHz.Additionally,toallowforadequatephasegaininthecompensationnetwork,thetheclosedloopcrossoverfrequencyshouldbeatleast30percenthigherthantheLCcornerfrequency.Thislimitstheminimumcapacitorvaluefortheoutputfilterto:
K2C)1
OUT2pƒCOLOUT
whereNCisthenumberofoutputcapacitorsin
parallel.
ThemaximumESRoftheoutputcapacitorisdeterminedbytheamountofallowableoutputrippleasspecifiedintheinitialdesignparameters.TheoutputripplevoltageistheinductorripplecurrenttimestheESRoftheoutputfiltersothemaximumspecifiedESRaslistedinthecapacitordatasheetisgivenbyEquation16:
ESRMAXN
C
ǒVIN(MAX) LV
OUT
F
SW
0.8
VIN(MAX))VOUTOUT
ǒǓǓ pVp)p(MAX)
(16)
Where∆Vp-pisthedesiredpeak-to-peakoutput
ripple.Forthisdesignexample,two100-µFceramicoutputcapacitorsarechosenforC2andC10.TheseareTDKC3225X5R0J107M,ratedat6.3VwithamaximumESRof2mΩandaripplecurrentratinginexcessof3A.ThecalculatedtotalRMSripplecurrentis161mA(80.6mAeach)andthemaximumtotalESRrequiredis43mΩ.Theseoutputcapacitorsexceedtherequirementsbyawidemarginandwillresultinareliable,highperformancedesign.itisimportanttonotethattheactualcapacitanceincircuitmaybelessthanthecatalogvaluewhentheoutputisoperatingatthedesiredoutputof3.3V.
OthercapacitortypesworkwellwiththeTPS54550,dependingontheneedsoftheapplication.
COMPENSATIONCOMPONENTS
TheexternalcompensationusedwiththeTPS54550allowsforawiderangeofoutputfilterconfigurations.Alargerangeofcapacitorvaluesandtypesofdielectricaresupported.Thedesignexampleusestype3compensationconsistingofR1,R3,R5,C6,C7andC8.Additionally,R2alongwithR1formsavoltagedividernetworkthatsetstheoutputvoltage.ThesecomponentreferencedesignatorsarethesameasthoseusedintheSWIFTDesignerSoftware.Thereareanumberofdifferentwaystodesignacompensationnetwork.Thisprocedureoutlinesarelativelysimpleprocedurethatproducesgoodresultswithmostoutputfiltercombinations.Use
(
)(14)
WhereKisthefrequencymultiplierforthespreadbetweenfLCandfCO.Kshouldbebetween1.3and15,typically10foronedecadedifference.Foradesiredcrossoverof13kHzanda6.8-µHinductor,theminimumvaluefortheoutputcapacitorisaround
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oftheSWIFTDesignerSoftwarefordesignswithunusuallyhighclosedloopcrossoverfrequencies,lowvalue,lowESRoutputcapacitorssuchasceramicsorifthedesignerisunsureaboutthedesignprocedureisrecommended.
WhendesigningcompensationnetworksfortheTPS54550,anumberoffactorsneedtobeconsidered.Thegainofthecompensatederroramplifiershouldnotbelimitedbytheopenloopamplifiergaincharacteristicsandshouldnotproduceexcessivegainattheswitchingfrequency.Also,theclosedloopcrossoverfrequencyshouldbesetlessthanonefifthoftheswitchingfrequency,andthephasemarginatcrossovermustbegreaterthan45degrees.Thegeneralprocedureoutlinedhereproducesresultsconsistentwiththeserequirementswithoutgoingintogreatdetailaboutthetheoryofloopcompensation.
FirstcalculatetheoutputfilterLCcornerfrequencyusingequationEquation17:
1ƒ
LC2p)LC
OUTOUT(17)Forthedesignexample,fLC=4315Hz.
Theclosedloopcrossoverfrequencyshouldbe
greaterthanfLCandlessthanonefifthoftheswitchingfrequency.Also,thecrossoverfrequencyshouldnotexceed50kHz,astheerroramplifiermaynotprovidethedesiredgain.Forthisdesign,acrossoverfrequencyof13kHzwaschosen.Thisvalueischosenforcomparativelywideloopbandwidthwhilestillallowingforadequatephaseboosttoinsurestability.
NextcalculatetheR2resistorvaluefortheoutputvoltageof3.3VusingEquation18:
R1 0.891R2V)0.891OUT(18)ForanyTPS54550design,startwithanR1valueof
1.0kΩ.R2isthen374Ω.
Nowthevaluesforthecompensationcomponentsthatsetthepolesandzerosofthecompensationnetworkcanbecalculated.AssumingthatR1>R5andC6>C7,thepoleandzerolocationsaregivenbyequations19through22:
1
Z12pR3C6
1ƒ
Z22pR1C8
1ƒ
P12pR5C8
1ƒ
P22pR3C7ƒ
(19)(20)(21)(22)
Additionallythereisapoleattheorigin,whichhasunitygainwiththefollowingfrequency:
1ƒ
INT2pR1C6(23)Thispoleisusedtosettheoverallgainofthecompensatederroramplifieranddeterminestheclosedloopcrossoverfrequency.
ThereareanumberofpopularwaystodesignType3compensationnetworks.Thetheorybehindthesecalculationsisbeyondthescopeofthisdocument.Itisalwaysbesttotouseanycalculatedcompensationvaluesasthebasisforaninitialdesign,andthenverifytheactualclosedloopresponse.Theinitialvaluesmaythenbeadjustedtosuittheindividualdesignrequirements.TheSWIFTsoftwaredesigntoolcanalsobeusedtoprovideanintialcircuitdesign.
Inthiscircuit,thefirstcompensationzerowassetatapproximatelyonehalftheLCcornerfrequency,withthesecondzeroslightlybelowthattoincreasethephasegainpriortothedoublepoleoftheLCoutputfilter.AttheLCcornerfrequencytheoverallphaseresponserapidlydropsby180degrees,soitisimprtanttoincreasetheinitialphaseof90degreespriortotheLCcorner.
Thetwocompensationpolesaresethighenoughtotonotcauselossofphasemarginattheclosedloopcrossoverandlowenoughtonotcausetheerroramplifiergaintoexceedtheunitygainbandwidthlimitoftheinternaloperationalamplifier.Theintegratorfrequencyisthenchasentosettheoverallgainandcrossoverfrequency.Thisresultsfrequencies:fZ1=2340HzfZ2=1591HzfP1=120kHzfP2=159kHzfINT=234Hz
in
the
following
pole
and
zero
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ThemeasuredoverallloopresponseforthecircuitisgiveninFigure5.Notethattheactualclosedloopcrossoverfrequencyishigherthanintendedatabout25kHz.thisisprimarilyduetovariationintheactualvaluesoftheoutputfiltercomponentsandtolerancevariationoftheinternalfeedforwardgaincircuitry.Overallthedesignhasgreaterthan60degreesofphasemarginandwillbecompletelystableoverallcombiationsoflineandloadvariability.
SinceR1isgivenas10kΩandthecrossoverfrequencyisselectedas13kHz,thedesiredfINTcanbecalculatedwithEquation24:
10–0.9 ƒ
COƒ)
INT2(24)AndthevalueforC6isgivenbyEquation25:
1C6
2pR1ƒ
INT
C7
18pR3ƒ
CO
(30)
Notethatcapacitorsareonlyavailableinalimitedrangeofstandardvalues,sotheneareststandardvaluehasbeenchosenforeachcapacitor.ThemeasuredclosedloopresponseforthisdesignisshowninFigure30.
BIASANDBOOTSTRAPCAPACITORS
EveryTPS54550designrequiresabootstrapcapacitor,C3andabiascapacitor,C4.Thebootstrapcapacitormustbe0.1µF.ThebootstrapcapacitorislocatedbetweenthePHpinsandBOOTpin.Inaddition,a24ohmresistorisplacedinserieswiththebootstrapcapacitor.ThisresistorisusedtoslowdowntheleadingedgeofthehighsideFETturnonwaveform.Usingthisresistorwilldramaticallydecreasetheamplitudeoftheovershootontheswtchingnode.ThebiascapacitorisconnectedbetweentheVBIASpinandAGND.Thevalueshouldbe1.0µF.BothcapacitorsshouldbehighqualityceramictypeswithX7RorX5Rgradedielectricfortemperaturestability.Theyshouldbeplacedasclosetothedeviceconnectionpinsaspossible.
(25)
Thefirstzero,fZ1,islocatedatonehalftheoutputfilterLCcornerfrequency,soR3canbecalculatedfromEquation26:
1R3
pC6ƒ
LC(26)Thesecondzero,fZ2,islocatedattheoutputfilterLC
cornerfrequency,soC8canbecalculatedfromEquation27:
1C8
2pR1ƒ
LC(27)Thefirstpole,fP1,islocatedtocoincidewiththe
outputfilterESRzerofrequency.ThisfrequencyisgivenbyEquation28:
1ƒ
ESR2pRC
ESROUT(28)whereRESRistheequivalentseriesresistanceofthe
outputcapacitor.
Inthiscase,theESRzerofrequencyis35.4kHz,andR5canbecalculatedfromEquation29:
1R5
2pC8ƒ
ESR(29)Thefinalpoleisplacedatafrequencyabovethe
closedloopcrossoverfrequencyhighenoughtonotcausethephasetodecreasetoomuchatthecrossoverfrequencywhilestillprovidingenoughattenuationsothatthereislittleornogainattheswitchingfrequency.ThefP2polelocationforthiscircuitissetto4timestheclosedloopcrossoverfrequencyandthelastcompensationcomponentvalueC7canbederivedfromEquation30:
LOW-SIDEFET
TheTPS54550isdesignedtooperateusinganexternallow-sideFET,andtheLSGpinprovidesthegatedriveoutput.ConnectthedraintothePHpin,thesourcetoPGND,andthegatetoLSG.TheTPS54550gatedrivecircuitryisdesignedtoaccommodatemostcommonn-channelFETsthataresuitableforthisapplication.TheSWIFTDesignerSoftwarecanbeusedtocalculateallthedesignparametersforlow-sideFETselection.Therearesomesimplifiedguidelinesthatcanbeappliedthatproduceanacceptablesolutioninmostdesigns.TheselectedFETmustmeettheabsolutemaximumratingsfortheapplication:
Drain-sourcevoltage(VDS)mustbehigherthanthemaximumvoltageatthePHpin,whichisVINMAX+0.5V.
Gate-sourcevoltage(VGS)mustbegreaterthan8V.Draincurrent(ID)mustbegreaterthan1.1xIOUTMAX.Drain-sourceonresistance(rDSON)shouldbeassmallaspossible,lessthan30mΩisdesirable.LowervaluesforrDSONresultindesignswithhigherefficiencies.Itisimportanttonotethatthelow-sideFETontimeistypicallylongerthanthehigh-sideFETontime,soattentionpaidtolow-sideFETparameterscanmakeamarkedimprovementinoverallefficiency.Totalgatecharge(Qg)mustbelessthan50nC.Again,lowerQgcharacteristicsresultinhigherefficiencies.
22
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
Additionally,checkthatthedevicechoseniscapableofdissipatingthepowerlosses.
Forthisdesign,aVishaySiliconixSI711020-Vn-channelMOSFETisusedasthelow-sideFET.ThisparticularFETisspecificallydesignedtobeusedasalow-sidesynchronousrectifier.
POWERGOOD
TheTPS54550isprovidedwithapowergoodoutputpinPWRGD.Thisoutputisanopendrainoutputandisintendedtobepulleduptoa3.3-Vor5-Vlogicsupply.A10-kΩ,pull-upresistorworkswellinthisapplication.Theabsolutemaximumvoltageis6V,socaremustbetakennottoconnectthispull-upresistortoVINifthemaximuminputvoltageexceeds6V.
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TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
www.ti.com
APPLICATIONCURVES(seeFigure29)
LOOPRESPONSE
7060210180LOADREGULATION
0.150.150.1LINEREGULATION
Phase50401500.1IO= 2.5AIO= 5ALoad Regulation - %120Phase - DegreesG - Gain - dB3020100-10-20-3010900.05VI= 15 V0-0.05VI= 12 VVI= 9 VVI= 6 VOutput Regulation - %0.050-0.05-0.1See Figure 17-0.1567891011121314151617VI- Input Voltage - V
IO= 0AGainVI= 12 V,VO= 3.3 V,IO= 2.5A,fS= 700 kHz1001 k10 kf - Frequency - Hz
100 k60300-30-60-901 MVI= 17 V-0.1-0.1500.5
11.522.533.544.55
IO- Output Current -A
Figure30.EFFICIENCY
vs
OUTPUTCURRENT
100Figure31.
INPUTRIPPLEVOLTAGE
Figure32.
OUTPUTRIPPLEVOLTAGE
VI(Ripple)= 100 mV/div (ac) coupled
VO= 10 mV/div (ac) coupled
9590See Figure 17
V(PH)= 2 V/div
See Figure 17
V(PH)= 2 V/div
85807501234IO- Output Current -A
5VI= 7 V, VO= 3.3 V, IO= 5A, fS= 700 kHz
Time - 500 ns/div
VI= 7 V, VO= 3.3 V, IO= 5A, fS= 700 kHz
Time - 500 ns/div
Figure33.
LOADTRANSIENTRESPONSE
VI= 12 V, VO= 3.3 V,fS= 700 kHz,See Figure 17
VO= 50 mV/div (ac) coupled
Figure34.
POWERUP
VI= 5 V/div
Figure35.
VO= 2 V/div
IO= 1A/div,1.25Ato 3.75AStep
Time - 200ms/div
Time - 5 ms/div
Figure36.Figure37.
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PACKAGEOPTIONADDENDUM
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18-Jul-2006
PACKAGINGINFORMATION
OrderableDeviceTPS54550PWPTPS54550PWPG4TPS54550PWPRTPS54550PWPRG4
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVE
PackageTypeHTSSOPHTSSOPHTSSOPHTSSOP
PackageDrawingPWPPWPPWPPWP
PinsPackageEcoPlan(2)
Qty16161616
9090
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEAR
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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