UX3328 datasheet_V2.1

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

General Description

The UX3328 is an ONU intelligent limiting amplifier and burst mode laser driver for PON

applications. The limiting amplifier can be operated in 2.5Gbps. The laser driver can be operated in 1.25Gbps/2.5Gbps burst mode and continous mode. The UX3328 could be applied to GEPON, GPON and BPON. It can be set by IIC from external EEPROM or MCU. The UX3328 has DDM functions. It can read and calibrate VCC, temperature, Ibias, transmitter power, receiver power.

Features

Laser driver

Ibias current up to 100 mA; Imod current up to 80 mA; Burst on/off time < 5 ns;

TX SD delay time < 100ns or < 400ns, could be programmed; Digital APC and fast start-up function in burst mode;

Open loop with temperature look up table for Ibias and Imod; Supports 0dB, -3dB, -6dB APC power leveling settings; LDD has low power mode (sleep mode).

Limiting Amplifier

4 mV input sensitivity at 2.5Gbps; Selectable bandwidth and output swing; Signal detection and Jam functions; LA has low power mode (sleep mode).

Digital interface

Programmable IIC interface;

Build in Digital Diagnostic Monitor processor; Device settings stored in external EEPROM; With a DA output for APD control.

Applications

BPON, GEPON, GPON SFF/SFP modules Digital Video

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

Pin Configuration

283231SCL_EGND13029IROPVDD127SDA_EVDD1GND1LAONLAOPSDASCLRREFDAO12345678LOS_SDLAIPLAIN262524VDD3GND2LDON23222120191817UX3328TX_DISABLETX_FAULTGND2BENPLDIPLDINBENNMD16LDOPTX_SDOVDD2BIASNBIASP1011121314159Figure 1. Pin configuration QFN32

1 Ordering Information

UX3328, QFN32, 5mm×5mm

2 Pin Description

PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

NAME SDA_E VDD_1 GND_1 LAON LAOP SDA SCL RREF TX_FAULT TX_DISABLE LDIP LDIN GND2 BENP BENN MD DESCRIPTION IIC master mode data interface, internal 10Kohm pull-up Limiting Amplifier power supply Limiting Amplifier ground Limiting Amplifier signal output Limiting Amplifier inverted signal output IIC slave mode data interface IIC slave mode clock interface External reference resistor, external 10Kohm pull-down Transmitter fault alarm, external 4.7K~10K ohm pull-up Transmitter disable, inner 20K ohm pull-up Transmitter signal input Inverted transmitter signal input Transmitter and digital ground Burst signal non-inverse input Burst signal inverse input Monitor photodiode input Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 17 18 19 20 21 22 23 24 25 BIASP BIASN VDD2 TX_SDO LDOP LDON GND2 VDD3 DAO Transmitter bias output Inverted transmitter bias output Transmitter power supply Transmitter state indication output Transmitter signal output Transmitter signal output Transmitter and digital ground Digital power supply 8 bit DA current output, with external resistor to gnd or vdd for APD control Limiting Amplifier signal lost alarm, external 4.7K~10K ohm pull-up ROSA input optical power monitor input Limiting Amplifier inverted signal input Limiting Amplifier signal input Limiting Amplifier ground Limiting Amplifier power supply IIC master mode clock interface, internal 10Kohm pull-up 26 27 28 29 30 31 32 LOS_SD IROP LAIN LAIP GND1 VDD1 SCL_E 3 Key Specifications

3.1 Absolute Maximum Ratings

Symbol VCC TSTO TJUN ESD Parameter Supply voltage Storage temperature Max junction temperature HBM model Min. -0.5 4 Typical Max. 4.5 150 140 Units. V ℃ ℃ KV Device not guaranteed to meet specifications, permanent damage may be incurred by operating beyond these limits.

3.2 Continuous Ratings

Symbol VCC ICC TOPE Parameter Supply voltage Current consumption * Operating temperature Min. 2.97 -40 Typical 3.3 100 25 Max. 3.63 130 85 Units. V mA ℃ *: excluding bias and modulation current.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

3.3 Limiting Amplifier

Symbol SEN IOVER RIN VIN_CM f-3DB,LOW TEDGE VSW TJ ROUT Noise PSRR VM Bandwidth TLOSS Hys VTH Parameter Differential input sensitivity Differential overload input Differential input resistance Input common mode voltage Input low cutoff frequency Output rising / falling time (20%~80%) Differential output amplitude Total jitter Differential output resistance Input referred noise Power supply rejection ratio* Differential mute output** 3dB frequency Loss detecting time constant Optical hysteresis ratio OMA Loss signal detecting threshold ROP Receive optical power range Min. 2000 80 500 700 80 25 1000 4 0.5 -35 Typical 4 100 1.9 10 100 600 800 50 100 70 40 15 2 3 Max. 120 700 900 120 15 2500 100 50 10 0 Units. mVpp mVpp ohm V KHz ps mVpp ps ohm uV dB mV MHz us dB dB mVpp uA dBm Range_rop *: f<2MHz **: when squelch function is enabled and input signal is less than threshold level.

3.4 Transmitter

3.4.1 Transmitter Inputs: LDIN/LDIP, BENN/BENP

Symbol VID VCM Parameter Differential input swing The DC voltage of input Min. 200 1200 Typ. 0.6VDD Max. 2400 Units. mV VDD-200 mV 3.4.2 Laser Driver

Symbol IBIASMAX Parameter Maximum bias current Min. Typ. 100 Max. Units. mA Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications IBIASOFF IMODMAX IMODOFF TR/TF Bias shutdown current Maximum modulation current Modulation shutdown current 80 70 100 100 uA mA uA ps Electrical 20% to 80% rise/fall time, measured with 15Ω effective termination, Imod=40mA Total jitter Photodiode capacitance Photodiode input sink current 0.02 TJ IMD CMD 60 3 100 ps mA pF 3.4.3 Burst Mode Timings

Symbol Parameter Min. Typ. Max. Units. Burst enable/disable delay time, assertion of BEN to 90% of desired Ibias + Imod, de-assert of BEN to 10% of settled Ibias + Imod Burst on time and burst 200 off time Time from start to get mean power, and fast 1ns start disabled, Apcfsst, table 3, 83(7)h=0 TON Time from start to get mean power, and fast start enabled, Apcfsst, table 3, 83(7)h =1 Time from ben on to TX_SDO high, when SD_C, table 3, 82(6)h=0 TTX_SDON Time from ben on to TX_SDO high, when SD_C, table 3, 82(6)h =1 TBENONDELAY/ TBENOFFDELAY 4 12 ns TBENON/ TBENOFF ns 70 ms 1us or 3 bursts when fstclk1_2, table 3, 82(0)h=0, 2us or 6 bursts when fstclk1_2, table 3, 82(0)h =1 60 100 ns 200 300 ns

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications TTX_SDOFF Time from ben off to TX_SDO low, when SD_C, table 3, 82(6)h =0 Time from ben off to TX_SDO low, when SD_C, table 3, 82(6)h =1 60 100 ns 200 300 ns 3.4.4 Interface Signals

Symbol VHIGH VLOW VFAULT_HIGH VFAULT_LOW Parameter TX_Disable input high TX_Disable input low TX_Fault output high voltage TX_Fault output low voltage Min. 2 2 Typ. Max. 0.8 0.8 Units. V V V V 3.4.5 Safe Logic Timings

Symbol TINIT Parameter Min. Typ. Max. 150 Units. ms Time to initialize from power on or negation of TX_Fault using TX_Disable Time from falling edge of TX_Disable to when the modulation optical output rises above 90% of nominal, when fast start disable Time from falling edge of TX_Disable to when the modulation optical output rises above 90% of nominal, when fast start enabled TOFF Time from rising edge of TX_Disable to when the optical output falls below 10% of nominal TON 70 ms 1us or 3 bursts when fstclk1_2, table 3, 82(0)h=0, 2us or 6 bursts when fstclk1_2, table 3, 82(0)h =1 1 us

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications TFAULT TRESET Time from TX_Fault fault to 10 us us Time TX_Disable must be 10 held high to reset TX_Fault 3.5 2-Wire Serial Interface 3.5.1 AC Electrical Characteristics

Parameter SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock Symbol Comment Min. fSCL tLOW tHIGH 0 1.3 0.6 0.6 0.6 0 100 Typ. Max. 400 - - - - 0.9 - 300 300 - 10 Units. kHz us us us us us ns ns ns us us pF Set-up time for a repeated tSU:STA START condition Hold time (repeated) START tHD:STA condition Data hold time Data set-up time tHD:DAT tSU:DAT Rise time of both SDA and SCL tR signals Fall time of both SDA and SCL tF signals Set-up time for STOP condition tSU:STO Bus free time between a STOP tBUF and START condition Capacitance for each I/O pin CI 20+0.1Cb 20+0.1Cb 0.6 0.6 -

Figure 2. -SDA and SCL bus timing

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

3.5.2 DC Electrical Characteristics

Parameter Low level voltage Symbol Comment input VIL 3mA sink current Min. -0.5 0.7VDD 0 Typ. Max. 0.3VDD Units. V High level input VIH voltage Low level voltage O/P VOL VDD+0.5 V 0.4 10 250 10 V uA ns pF I/P current each I/O II pin Output fall time tOF from VIHmin to VILmax Capacitance each I/O pin for CI 0.1VDD3.5.3 LVTTL I/O Pins

Parameter LVTTL voltage out high LVTTL voltage out low LVTTL voltage in high LVTTL voltage in low Internal resistance Comment Min. Typ. Max. Units. External 4.7k to 10k VDD-0.5 pullup External 4.7k to 10k 0 pullup Internal pullup Internal pullup 2.0 0 10 VDD+0.3 V 0.5 V VDD+0.3 V 0.8 V kΩ pull-up SDA_E, SCL_E

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

4 Functional description 4.1 Overview

LAIPLAINIROPSDA_ESCL_ESDASCLDAOLDOPLDONBIASPBIASNTX_SDOLALAOPLAONLOS_SDIIC SIIC MDACCONTROLLER®ISTORSMONITORS&TEMPSENSORCBIASRREFTX_FAULTSAFETYTX_DISABLELDDLDIPLDINBENPBENNMD

Figure 3. UX3328 function overview

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

4.2 Limiting Amplifier 4.2.1 Architecture

DC RESTORELAIPLAINGAINCMLLAOPLAONIROPPEAK DETECTORLOS BUFFERLOS-SDCONTROL LOGIC

Figure 4. Limiting Amplifier function overview

4.2.2 Limiting Amplifier Features

The limiting amplifier of UX3328 mainly consists of six blocks, which are multi-stages gain block, CML logic output buffer, dc offset cancellation block, peak detector block, LOSS output buffer and control logic block.

The gain block consists of several high gain amplifier stages. To optimize the sensitivity performance for different input signal bit rate operation, the bandwidth is programmable, which can be programmed by setting the RX_CTRL register Bwd, table 3, 8D(6-5)h. The signal channel polarity also can be switched by setting the RX_CTRL register Dapol, table 3, 8D(4)h.

The CML output buffer block provides a high speed standard CML logic output interface with 50ohm output impedance. There are two output limiting amplitude levels can be selected by setting RX_CTRL register Rx_limscope, table 3, 8D(7)h. UX3328 also supports selectable squelch function, when setting RX_CTRL register Squ, table 3, 8B(2)h, as “1”,

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

the CML output will be disabled when the input signal is smaller than the pre-programmed

threshold level. In such case, a logical “0” is output on output.

UX3328 provides two methods to detect the lost signal, OMA (optical modulation amplitude) and ROP (receive optical power). If RX_CTRL register Losel, table 3, 8B(1)h is set as “0”, then the OMA method is selected. If RX_CTRL register Losel, table 3, 8B(1)h is set as “1”, then the ROP method is selected. No matter which method is selected, the loss signal threshold value both can be modified by programmed register RxAlarmDAC, table 3, 8Ch. There are two levels of loss detecting hysteresis ratio selectable for customers. If RX_CTRL register hysel, table 3, 8B(0)h is set to “0”, then the optical hysteresis ratio of 2dB is selected; if RX_CTRL register hysel, table 3, 8B(0)h is set to “1”, then the optical hysteresis ratio of 3dB is selected. The loss output polarity is controlled by RX_CTRL register Lopol, table 3, 8B(3)h. If RX_CTRL register Lopol, table 3, 8B(3)h is set to “0”, then when the input signal is smaller than threshold value, the loss asserts and outputs “high” logic. If RX_CTRL register Lopol, table 3, 8B(3)h is set to “1”, then when the input signal is smaller than threshold value, the loss asserts and outputs “low” logic.

The Figure 5 and Figure 6 indicate the assert and deassert point against the RxAlarmDAC, table 3, 8Ch value. In figure 5, the UX3328 uses OMA to detect the lost signal. The Y axis indicates the differential input amplitude when the RX LOS detection assert or deassert, the X axis indicates the decimal value of the RxAlarmDAC, table 3, 8Ch. In figure 6, the UX3328 uses ROP to detect the lost signal. The Y axis indicates the RX POWER level when the RX LOS detection assert or deassert, the X axis indicates the decimal value of the RxAlarmDAC, table 3, 8Ch.

Assert/Deassert VS. RX_ALARMDAC180.00160.00Assert/Deassert (mV)140.00120.00100.0080.0060.0040.0020.000.0011632488096128160196RX_ALARMDACAssertDeassert(HYS=2dB)Deassert (HYS=3dB)

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

Figure 5. Limiting Amplifier OMA LOS detection

Assert/Deassert VS. RX_ALARMDAC-10-12-14-16-18-20-22-24-26-28-30-32-34-36-38-4048163246128200RX_ALARMDACAssert/Deassert (dBm)AssertDeassert (HYS=2dB)Deassert (HYS=3dB) Figure 6. Limiting Amplifier ROP LOS detection

The LA in UX3328 has sleep mode. If std, table 3, 8D(0)h is set to “0”, then LA is in normal work state; if std, table 3, 8D(0)h is set to “1”, then LA is in sleep mode, and the current of LA will be shut dwon.

4.2.3 Voltage Reference

The UX3328 includes a temperature stable 1.27V reference source which provides the bias for the internal analog circuitry. The voltage reference requires an external 10KΩ, 1% precision resistor connected between pin 8 RREF and ground.

4.3 Laser Driver Features

The laser driver input buffer provides the necessary drive to the laser driver output stage. It includes an internal high impedance bias network and is designed to be DC or AC-coupled. For high frequency applications an external termination network must be implemented.

The laser driver output is designed to drive lasers in common anode configuration using DC or AC-coupling. In burst mode operation DC-coupling must be used.

The data polarity of the laser driver could be changed by setting Inpolsw, table 3, 82(2)h.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications The burst enable polarity of the laser driver could be changed by setting BEN_pch, table 3,

(2)h. The DCD of the output eyediagram could be adjusted by setting Vdcdc, table 3, 83(4-0)h.

4.3.1 Modulation Current Control

The modulation current can be either set by a constant register value or controlled by a temperature indexed look-up Table (TLUT) or by interior temperature compensation. If ModLutEn, table 3, 82(3)h is set to 0, then Imod is set by a constant in Imodc, table 3, 88h.

If ModLutEn, table 3, 82(3)h is set to 1, then Imod is set by MOD TLUT, Table 5, 80-BBh. The TLUT is indexed by the temperature ADC. The temperature ADC could be saw in TEMP_DATA, table 3, C6h. And the index is given by the integer of

Index =1 while temperature ADC<76

Index = (temperature ADC – 73)/3 while 76231

In every index there are 8 bits Imod current DAC.

The values of TLUT reside in EEPROM, and are transferred at start up to on-chip registers.

LDIPInputBufferModDriverLDOPLDINLDONModLutEntable 3, 82(3)HMOD TLUT, table5, Temperaturelook up tableImodc table 3, 88h10+ImodDACImt, table 3, 86(4-0)h

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

Figure 7 -Imod generation

The active setting of Imod current DAC can be read at Imod, table 3, C3h. Parameter Imod_dac Comments Typical Step Size DAC Range 0 to 88 mA Operational Range 0 to 80 mA Imod current 0.345mA(+/-0.173mA) DAC (8 bits) Tab 1 Imod current DAC Characteristics Imt, table 3, 86(4-0)h sets the interior temperature compensation of Imod. If Imt[4:0] is set to 00000, there is no compensation to Imod. If Imt[4:0] is set to 11111, Imod has largest compensation of temperature.

In any setting of Imod, the value of Imod would be monitored and could be read by AMUX output.

4.3.2 Bias Current Control

The bias current can be set with open loop or closed loop. In either mode the Ibias would be monitored and could be read by AMUX output. The bias current is controlled by an 8 bits DAC, and the setting of this DAC can be read at BIASCT_R, table 3, BCh. Parameter Ibias_dac

Comments Typical Step Size DAC Range 0 to 100 mA Operational Range 0 to 90 mA Ibias current 0.392mA(+/-0.196mA) DAC (8 bits) Tab 2 Ibias current DAC Characteristics

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

MDM, table 3, 83(6-5)hMDImdx mImdmcompIapcset, table 3, 85hImd DACInitialBias10Bsluten, table 3, 82(5)hBiaspre, table 3, 87hConstant BiasBIAS TLUT01BiasCT_R,table 3, BChADC andAMUX0DigitalControl1IbiasDACBiasDriverBIASPBIASNCL_Oln, table 3, 82(4)hApcfsst, table 3, 83(7)h(BiasMax,table 3, 84h)/2TX Bias -65hFigure 8. Ibias generation

4.3.2.1 Open Loop

If CL_OLn, table 3, 82(4)h is set to 0, the bias current is set in open loop mode. The bias current can be either set by a constant register value biaspre, table 3, 87h while Bsluten, table 3, 82(5)h is set to 0, or set by a temperature indexed lookup Table (TLUT) while Bsluten, table 3, 82(5)h is set to 1.

The BIAS TLUT, Table 4, 80-BBh is indexed by the temperature ADC. The index is given by the integer of

Index =1 while temperature ADC<76

Index = (temperature ADC – 73)/3 while 76Index =60 while temperature ADC>231

The active setting of Ibias current DAC can be read at biastlut, table 3, C2h.

4.3.2.2 Closed Loop

If CL_OLn, table 3, 82(4)h is set to 1, the bias current is set in closed loop mode. The average output power of the laser is controlled by a digital mean power control loop. The feedback to the control loop is provided by a monitor photodiode connected to MD pin. The current from the monitor photodiode Imd is scale-up or scale-down (set by MDM, table 3, 83(6-5)h ) to Imdm and then compares with a reference current Iapcset, table 3, 85h. When

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

the APC is stable Imdm will be very close to Iapcset. How to set Iapcset and MDM are determined

by the range of the target monitor photodiode current Imd. The full range of Iapcset is 223uA in typical. Imd range (uA) 0-50 0-200 0-800 0-3000 MDM[1:0] 00 01 10 11 Imdm (0-200uA) Imd*4 Imd Imd/4 Imd/16 Operational Range 0 to 200 uA The Iapcset is a 8 bits DAC. Parameter Iapcset_dac Comments Typical Step Size DAC Range 0 to 223 uA Imd current 0.875uA(+/-0.438uA) DAC (8 bits) The comparator in digital APC is a hysteresis comparator, and its hystersis range Irange can be set by Apcrange, table 3, 81(2-1)h. The range is set by several microamps of Iapcset. Apcrange[1:0] Irange 00 1.75uA 01 3.5uA 10 7uA 11 14uA In typical situation, Irange should be set as small as possible for good accuracy of Imd setting. But if the Irange is set too small, it would add some jitter to output eye diagram. So the Irange should be chosen properly.

The time constant of the digital mean power control loop (Tapcrc) is controlled by MDC, table 3, 86(6-5)h. MDC[1:0] Tapcrc (us) 00 5 01 15 10 30 11 60 The digital APC has inner clock (typical frequency is 5KHZ).

The UX3328 has APC scale function. If this function is used, then Iapcset and Imod will be scaled down in the same proportion. This function is set by APCSCALE[2:0], table 3, 81(7-5)h.

APCSCALE[2:0] 000 001 010

Iapcset and Imod ×1 ×0.8 ×0.667

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

011 100 101 110 111

×0.5 ×0.4 ×0.33 ×0.287 ×0.25

4.3.2.3 Initial Start-up

There are two types of APC initial start-up in closed loop. If Apcfsst, table 3, 83(7)h is set

to 1, then fast start-up is enabled. If Apcfsst, table 3, 83(7)h is set to 0, then normal start-up is enabled.

If Apcfsst is set to 0, then it is initialed with normal start-up. The initial Ibias could load a constant from biaspre, table 3, 87h while Bsluten, table 3, 82(5)h=0 or from a BIAS temperature look up Table while Bsluten, table 3, 82(5)h=1.

In fast start-up mode, Apcfsst is set to 1. After power up, Starten, table 3, 81(0)h is set to 1, TX_Disable is set to low and while BEN is set to high, then the APC started. In the first 8 clocks the APC uses a fast clock which is set by Fstclk1_2, table 3, 82(0)h. When Fstclk1_2 is set to 1 then 5MHZ clock is chosen. And when Fstclk1_2 is set to 0 then 10MHZ clock is chosen. These 8 clocks are paused when BEN turns off the bias and modulation currents. At the first 8 clocks, the APC uses binary search sequence to get the mean power. During this period, the data path is disabled and modulation outputs balanced such than Imod/2 flows into both LDOP and LDON. The first bias current output is determined by BiasMax, table 3, 84h, which is an 8 bits binary code to set the safe maximum bias current. And the first Ibias DAC is set to BiasMax/2. In the following 7 clocks the APC will find out the target mean power. After that, the data path will be enabled, and the APC clock will change to normal clock.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

TX_DISABLE3.02.0( V )1.00.0BEN3.02.0( V )1.00.050mIBIAS30m( A )10m0mtime

Figure 9. Burst mode APC fast start-up

4.3.2.4 Burst Mode

In burst mode when pin BENP/BENN is set to low/high, the modulation and bias currents are turned off. When pin BENP/BENN is set to high/low, the modulation and bias currents are turned on again. The burst on/off timings are detailed in 3.4.3.

In burst mode, pin20 TX_SDO could indicate the laser diode state. The output level could be set to TTL or CMOS level. While CMOS_SEL, table 3, (1)h=1, the output is CMOS level. While CMOS_SEL, table 3, (1)h=0, the output is TTL level, and the pin20 should pull up a 4.7-10KΩ resistor to vdd for TX_SD function. When BENP/BENN is set to high/low the laser diode is turned on, and the monitor current Imd is high, then TX_SDO will set to high. Otherwise TX_SDO will set to low.

There is a high speed comparator in UX3328. The monitored current Imd is calculated to Imdm by MDM, table 3, 83(6-5)h, and then is compare to a reference current Imdsd. Imdsd could be set by Txsdset, table 3, 81(4-3)h and Iapcset, table 3, 85h. So even in open loop, if we want the TX_SD function to work normally, we should set Iapcset equal to the PD monitor current Imd. Txsdset[1:0] Imdsd 00 1/8 of Iapcset 01 2/8 of Iapcset 10 3/8 of Iapcset 11 4/8 of Iapcset The delay of TX_SD could be set by SD_C, table 3, 82(6)h. And this is detailed in 3.4.3.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

4.4 Laser Safety Features

The laser safety circuit monitors the device for potential faults. If a fault is detected then

the pin9 TX_FAULT will be asserted, and it will be latched even if the fault condition goes away. The latched fault can be cleared by restart power , or the pin TX_DISABLE is set to 1 and then to 0, or the register Soft TX Disable 6E(6)h is set to 1 and then to 0. The register bit TX_FAULT 6E(2)h reflects the status of the pin TX_FAULT. The register bit TX Disable State 6E(7)h is the state of input pin TX_DISABLE. The Soft TX Disable is “or”d with hard TX_DISABLE to control the laser drive. A transmit fault can be raised by the following:

1. After power on the supply monitoring circuit detects that the power supply voltage is <2.7V or >3.9V. Choose this as a fault condition should set Faultset[0], table 3, 8A(3)h=1, and this fault state is in Fault[0], table 3, BD(0)h.

2. The RREF monitoring circuit detects that this pin connects to VDD or GND or is floating. Choose this as a fault condition should set Faultset[1], table 3, 8A(4)h=1, and this fault state is in Fault[1], table 3, BD(1)h.

3. The output voltage monitoring circuit detects that the voltages of LDOP/LDON is smaller than 0.1V. Choose this as a fault condition should set Faultset[2], table 3, 8A(5)h=1, and this fault state is in Fault[2], table 3, BD(2)h.

4. The output voltage monitoring circuit detects that the voltages of BIASP/BIASN is smaller than 0.1V. Choose this as a fault condition should set Faultset[3], table 3, 8A(6)h=1, and this fault state is in Fault[3], table 3, BD(3)h.

5. BIAS > or = BIASMAX. Choose this as a fault condition should set Faultset[4], table 3, 8A(7)h=1, and this fault state is in Fault[4], table 3, BD(4)h.

If Ftshdnen, table 3, 82(1)h is set to 1, then the fault condition will also cause to shutdown the bias and modulation currents. If Ftshdnen, table 3, 82(1)h is set to 0, the fault condition will not shutdown the bias and modulation currents.

If Bsmaxprotect, table 3, 86(7)h is set to 1, in close loop mode, while the Ibias DAC counts to the value of BiasMax, table 3, 84h, then the counter can not be increased. It can only be held or reduced. If Bsmaxprotect, table 3, 86(7)h is set to 0, in this condition the Ibias DAC can either be increased or reduced.

The UX3328 LDD has some sleep mode. When Lpow, table 3, 82(7)h is set to 0, the laser driver operates in normal state. But when Lpow, table 3, 82(7)h is set to 1, the laser driver is disabled, and the current of the laser driver will be shut down.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

4.5 Burst Enable and TX Input Connection Options

The UX3328 supports various modes of interfacing to the transmit data (LDIP/LDIN) and

burst enable (BENP/BENN) inputs providing the signal voltage and common-mode voltage levels are within the valid range specified in 3.4.1. The input structure of UX3328 laser driver is shown as below.

UX3328vddR0r=16KR1r=16KR4R3LDIPBENPR5r=100M0M1LDINBENNR41r=24KR2r=24KI3idcgnd Figure 10. Laser driver input

4.6 Temperature Measurement

The UX3328 uses an on-chip temperature monitor and an 8-bit ADC to perform a temperature measurement once per 15mS. The measured ADC value can be read from register table 3, C6h.

The temperature monitor is connected with the 8-bit ADC through an analog multiplexer (AMUX). The measured PTAT (proportional to absolute temperature) voltage is presented to the 8-bit ADC by setting the AMUX address AMUX_ADDR<3:0> to 0000 table 3, B2(3-0)h.

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Figure 11. Temperature calibration functional block diagram

Figure 12. VTEMP voltage VS. Junction Temperature

Parameter Temperature VTEMP Voltage ADC Slope Accuracy Symbol T Vtemp Tacc Min. -40 500 Typical 1 Max. 120 1850 Units. ℃ mV ℃/bit ℃ 3

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

4.7 DA CURRENT OUTPUT

APD_CTRLtable 3, (0)hvddAPD TLUT, table6, Temperaturelook up tableAPD_DACC table 3, B0h01DAI_PNStable 3, 8A(0)hsourceDAsink10DAOAPD_DAC table 3, C5hgnd

Figure 13-DA block diagram

The UX3328 has a 8 bits DA current output. The DA output current can be set by a constant in APD_DACC, table 3, B0, or by a temperature look up Table APD TLUT, table 6, 80-BBh. If APD_CTRL, table 3, (0)h=1, the DA current is set by APD_DACC; if APD_CRTL, table 3, (0)h=0, the DA current is set by APD TLUT.

The APD TLUT is indexed by the temperature ADC. The temperature ADC could be seen in TEMP_DATA, table 3, C6h. And the index is given by the integer of

Index =1 while temperature ADC<76

Index = (temperature ADC – 73)/3 while 76Index =60 while temperature ADC>231

The DA current range is 0 to 171 uA, and its typical step is 0.67uA. Parameter Idao Comments Typical Step Size DAC Range 0 to 171 uA Operational Range 0 to 171 uA DA current 0.67uA(+/-0.33uA) output (8 bits) The DA current output can be a current source by setting DNI_PNS, table 3, 8A(0)h=0, or be a current sink by setting DNI_PNS, table 3, 8A(0)h=1. So for APD control, the pin 25 DAO should connect a resistor to ground or vdd, and the resistor should be smaller then 13KΩ.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

The DA block has sleep mode. DA_LPOW, table 3, 8B(7)h=0, DA works normally; DA_LPOW, table 3, 8B(7)h=1, DA is disabled, and its output is 0.

5 Control Interface

Host or MCU TWI Slave 2 RAM EEPROM TWI Master 1 Controller and DDM

Figure 14. Serial interfaces to RAM and the controller

The host communicates with the UX3328 via the slave Two Wire Interface(TWI) pins of the UX3328. When the data of the UX3328 is in need of storing to EEPROM, the UX3328 communicates with EEPROM via the master TWI pins of the UX3328.

5.1 Data Transfer Mechanisms

Two distinct data paths are identified in Figure 14.

When the UX3328 comes out of reset, the 2-wire serial slave interface is disabled. Only path 1 is active. The controller instructs the 2-wire serial master interface to attempt to transfer A0h and A2h register tables (A0 region, SFF-8472 diagnostics, user defined region, Device Settings, BIAS TLUT, MOD TLUT and APD TLUT) from the external EEPROM to RAM. If this is successful then the start pulse will be set and the UX3328 will enter in the normal operation. If the transfer fails, then the status alarm bits in the INIT_STATE (table 3, BFh) register will be set and the UX3328 will enter in the normal operation.

Regardless of the outcome, when the EEPROM read process is complete, the controller enables the 2-wire serial slave interface.

The value of the 2-wire serial slave interface address can be changed to a value other than

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

the default value of A0h and A2h(see datasheet register map in table 3, B1h).To change

The 2-wire serial slave interface address write a new value to this register. The two least significant bits will be saved as zeros, the saved address is thus a new A0h address. A2h is always slaveaddress+2. In the normal operation, the host or external MCU uses the 2-wire serial slave interface to write to or read from copies of A0 region, SFF-8472 diagnostics, user defined region, Device Settings, BIAS TLUT,MOD TLUT and APD TLUT held in RAM(path 2).

The UX3328 2-wire serial slave interface uses 8-bit addressing, which allows up to 256 bytes to be transferred on a given 2-wire slave address. However, since the UX3328

contains more than 256 bytes, a table scheme is used. The lower 128 bytes of the default A2h region are independent of the currently selected table. Byte 7Fh is the Table select byte. This byte determines which memory table will be accessed by the 2-wire interface when address locations 80h to FFh in the default A2 region are accessed. Valid values for the Table Select byte are shown in the table below. Table select byte(HEX) 00 01 03 04 05 06

Device setting(table 3) BIAS TLUT(table 4) MOD TLUT(table 5) APD TLUT(table 6) Tab 3. table select byte TABLE NAME User defined region(table 0) 5.2 Device Initialization Sequence

The Initialization Sequence is illustrated in Figure 15. The Data_Ready_Bar 6E(0)h bit in the STA_CTRL register indicates when data from the ADCs may be read after power up. It is first set to „1‟ before the 2-wire serial slave interface is enabled to indicate that the UX3328 is not ready. Once initialization is complete and the ADC data is ready, Data_Ready_Bar is cleared to „0‟. This event can be used by the external host/MCU as a signal that the UX3328 is ready for data to be uploaded from the UX3328 RAM.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

Power_onDelay 1msInitialize ramTransfer data from eeprom to ramNThree timesYNcommunicationsuccessYNYSet startenIntegrity successNTwo timesYSet fail flags and Reset ramSet fail flags and Reset ramInitialization complete and enter normal operation

Figure 15. the Initialization Sequence

5.2.1 Data Integrity Checking Addr table 3, 80h table 3, CBh

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications table 3, CAh EEPROMchksum the low order 8 bits of the sum of table 4,table 5 ,table 6 and addresses from 80h to B2h of table 3 Tab 4. the data integrity number On power-up, the UX3328 will attempt to load its RAM from the EEPROM. If the read fails due to a problem on TWI, such as a read not being correctly acknowledged and after trying three times, then the corresponding bits of the INIT_STATE register will be both set to „1‟ and initialization will be stalled. If the transfer is successful, then the integrity of the data will be checked. This process is carried out in the following sequence of events.

First, after communicating with EEPROM, the UX3328 will accumulate a 8 bit checksum for the A0h ram address range 00h to 3Eh. If this accumulated checksum does not compare correctly with the A0h ram address 3Fh and it tries two times, then dsfail0 will be set to „1‟. Second, the UX3328 will accumulate a 8 bit checksum for the A0h ram address range 40h to 5Eh. If this accumulated checksum does not compare correctly with the A0h ram address 5Fh and it tries two times, then dsfail1 will be set to „1‟.

Third, the UX3328 will accumulate a 8 bit checksum for the A2h ram address range 00h to 5Eh, If this accumulated checksum does not compare correctly with the A2h ram address 5Fh and it tries two times, then dsfail2 will be set to „1‟.

Four, two bytes read from addresses at table 3, 80h and CBh are compared against the values show in Tab 4. If there is a mismatch and it tries two times then dsfail3 is set to „1‟ and the initialization will be stalled.

If EEPROMIdentifier0 = AAh and EEPROMIdentifier1 = 55h, then the UX3328 will accumulate a 8 bit checksum for the A2h RAM of table 3, table 4, table 5 and table 6 region. If this accumulated checksum does not compare correctly with the EEPROMchksum byte, and if it tries two times, then dsfail3 will be set to „1‟ and initialization will be stalled. Once all checks are complete, if no alarms have been set then the hardware registers in the UX3328 are updated from the RAM,and the state machine will enable the 2-wire serial slave interface and enter the normal operation.

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5.3 Main Control LOOP

Enter normal operationMain loop funcion Check slave TWICheck adc flagRead/write operation to internal registers and set eepromflagsConduct ADC operation

Figure 16. main control loop function

After initialization，the main controller do the work as follows:

First, the controller transacts the communication with the host, writes data from host to ram or reads the data from ram to host and sets the EEPROM_FLAG byte for storing data to eeprom. To ensure the communication from the IIC, the operation is set to the highest priority in the main state machine;

Second, the controller transacts the operation of the following five real time reports: Supply Voltage, Temperature, Tx Bias current, Tx Output Power and Rx Input Power, including the storage, internal/external calibration and the setting of the alarm/warning flags；

After the UX3328 enters in the normal operation, the controller begins to monitor the IIC bus and the ADC operation. If the IIC bus is busy, the controller performs the operation of

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reading data from ram to host(writing data from host to ram). If the IIC bus is idle, the

controller will detect the flag of ADC operation. If the flag of ADC operation is detected, the controller conducts ADC operation. Otherwise, the controller waits for the flags of IIC and ADC operation. Meanwhile, the UX3328 waits for the bits of the EEPROM_GLAG byte. If one of the bits is set to „1‟, the UX3328 will transfer the corresponding data to EEPROM.

5.3.1 ADC_CTRL LOOP(Internal/External calibration、alarm and warning)

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Enter adc operationYDebug_enNInExt/InExtSelect debug mode,read data from ADCs and store dataRead ADCs and do internal calibrationRead ADCs and do external calibrationSet alarm/warning flagsIs it temperature valueYRead ADCs, index LUT using temperature ADC value and transfer value to the corresponding DACNQuit ADC operation

Figure 17. ADC control loop and DDM function

After the main state machine enter in the ADC controll operation, the controller check register bit „debug_en‟(table 3, B1h, bit 5). If the bit is „1‟, the main state machine sets the debug mode, reads data from ADCs, and store in the register DEBUG_DATA(table 3, C4h). If the bit is „0‟, the controller will check the register bits „In‟ and „Ext‟(table 3, B1h, bit6 and bit5).

If the register bit „Ext‟ is „1‟, the controller reads the ADCs and do the external calibration;

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If the register bit „In‟ is „1‟, the controller reads the ADCs and do the internal calibration. After the calibration, the controller reads the preset alarm/warning value of the five analog,

compares with the corresponding value which is internally measured and sets the alarm/warning flags.

An external host is required to apply the correct calibration slope and offset values to the UX3328 ADC DDM reports in order that the real time reports are meaningful. The internal calibration per the analogs is given by the following equation: ADCcal = Slope*ADCraw+offset

ADCcal:：the ADC value after calibration ADCraw ：the raw ADC value

Slope and offset are calculated values found in the corresponding tables. Tab 5 shows the memory locations that should be addressed on the 2-wire slave interface to access the various DDM ADC values. Location(hex) 8E-8Fh 90-91h 92-93h 94-95h 96-97h 98-99h 9A-9Bh 9C-9Dh 9E-9Fh A0-A1h Name TEMP_SLOPE TEMP_OFFSET VCC_SLOPE VCC_OFFSET BIAS_SLOPE BIAS_OFFSET TX_SLOPE TX_OFFSET RX_SLOPE RX_OFFSET Size(bit) 16 16 16 16 16 16 16 16 16 16 Tab 5. ADC DDM register locations When applied to GPON field, the UX3328 provides a multi-slope and multi-offset for the RX POWER calibration. Tab 6 shows which slope and offset will be used for the RX POWER calibration. The RX_COMP0, table 3, AC-ADh, and RX_COMP1, table 3, AA-ABh, is the two turning points of the calibration curve. ADC value ADCraw≥RX_COMP1(table 3, AA-ABh) RX_COMP0≤ADCrawTab 7 shows the signal comparison. Signal

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications Temperature Vcc Bias Tx power Rx power Two‟s complement Unsigned Unsigned Unsigned unsigned Tab 7. signal comparison All 8 bit or 12 bit ADC values are left aligned into the 16 bit registers with unused bits set to zero.

5.3.2 Calculating signal value

Temperature Bit Weights Most Significant Byte(60h) D7 SIGN D7 1/2 D6 D6 1/4 D5 32 D5 1/8 D4 16 D4 1/16 D3 8 D3 1/32 D2 4 D2 1/ D1 2 D1 1/128 D0 1 D0 1/256 Most Significant Byte(61h) Temperature conversion examples Temperature 25 1 0.004 -40 Binary HIGH BYTE 00011001 00000001 00000000 11011000 LOW BYTE 00000000 00000000 00000001 00000000 HEX HIGH BYTE 19 01 00 D8 LOW BYTE 00 00 01 00 To calculate the temperature, treat the two‟s complement value binary number as an unsigned binary number, then convert to decimal and divide by 256.if the result if great than or equal to 128,subtract 256 from the result.

Temperature: high byte: -128℃ to +127℃ signed; low byte: 1/256℃

Vcc/Bias/Tx power/Rx Power Bit Weights MSB LSB 215 27 214 26 213 25 212 24 211 23 210 22 29 21 28 20 The LSB = 100uV for Vcc, the LSB = 2uA for Bias, the LSB = 0.1uW for Tx Power and Rx Power when using factory default settings.

Vcc conversion examples

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications Vcc 3.3V 2.97V 3.63V Binary High byte 10000000 01110100 10001101 Low byte 11101000 00000100 11001100 Hex High byte 80 74 8D Low byte E8 04 CC To calculate Vcc, convert the unsigned 16-bit value to decimal and multiply by 100uV.

Bias conversion examples Bias 131 mA 100 uA Binary High byte 11111111 00000000 Low byte 11011100 00110010 Hex High byte FF 00 Low byte DC 32 To calculate Bias, convert the unsigned 16-bit value to decimal and multiply by 2uA.

Tx power and Rx power conversion examples Tx power and Rx power mW 5 0.1 dBm 7.0 -10 Binary High byte 11000011 00000011 Low byte 01010000 11101000 Hex High byte C3 03 Low byte 50 E8 To calculate Tx power and Rx power, convert the unsigned 16-bit value to decimal and multiply by 0.1uW.

Tab 8 shows the relationship between the temperature with the look-up table address which increases every 3 LSB over the 4Ch to B5h range and every 2 LSB over the B5h to E1h. Temperature CORRESPONDING LOOK-UP TABLE ADDRESS adc value (hex） <4C 4C 4F 52 55 58 5B - B5 B7

80h 80h 81h 82h 83h 84h 85h - A3h A4h Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications B9 - E1 >E1 A5h - BBh BBh Tab 8. Look-Up Table Address for corresponding Temperature Values

5.3.3 Password protection

Before attempting to read and write any of the bits or bytes from memory, it is important

to look at the memory map provided in a subsequent description to verify what level of password is required. Password protection applies both at slave default address A0 and A2 region.

The UX3328 uses two 4-byte passwords to achieve three levels of access to various memory locations. The three levels of access are:

User Access: This is the default state after power-up. It allows read access to standard monitoring and status functions.

Level 1 Access: This allows access to customer data table in addition to everything granted by User access. This level is granted by entering Password 1 (PW1).

Level 2 Access: This allows access to all memory, settings, and features, in addition to everything granted by Level 1 and User access. This level is granted by entering Password 2 (PW2).

To obtain a particular level of access, the corresponding password must be entered in the Password Entry(PWE) bytes located in the Main Device at 7Bh to 7Eh. The value entered is compared to both the PW1 and PW2 settings located in table 3, B3h to B6h and table 3, B7h to BAh, respectively, to determine if access should be granted. Access is granted until the password is changed or until power is cycled.

Writing PWE can be done with any level of access, although PWE can never be read. Writing PW1 and PW2 requires PW2 access. However, PW1 and PW2 can never be read, even with PW2 access.

On power-up, PWE is set to all 1s (FFFFh). As long as neither of the passwords are ever changed to FFFFh, then User access is the power-up default. Likewise, password protection can be intentionally disabled by setting the PW2 password to FFFFh.

The level of the UX3328 at slave default address A0 region and table 0 can be changed to a level other than the default level(see description of address at table 3, BBh). After the host writes datas to the UX3328，the main control state will detect the EERPOM_FLAG byte. If the corresponding bit is set to „1, the main control state will transfer datas to the external EEPROM with some certain cryptographic algorithm.

On the other hand, The value of the password level that was defined in A0 and user define region can be changed (see datasheet register map in table 3, BBh).To change The 2-wire serial slave interface address write a new value to this register.The level of password is

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described as following: Region A0 _lower A0_upper A2_lower User define CHIP SETTING Bias LUT MOD LUT APD LUT Write PW2/PW1/User PW1/ User PW2 PW1/ User PW2 PW2 PW2 PW2 Read User User User PW1/ User PW2 PW2 PW2 PW2 Tab 8. the level of password 6 2-wire Serial Interface

The UX3328 has a pair of 2-wire serial interfaces: a slave for interfacing to a host for

module setup and programming, and a master for interfacing to an external EEPROM and for device configuration after power up. Both interfaces communicate using the protocol described in this section.

6.1 Framing and Data Transfer

The 2-wire interface comprises a clock line (SCL) and a data line (SDA). When the bus is idle, master SDA and SCL are pulled high within the UX3328 by 10kΩ pull-ups and slave SDA and SCL are pulled high with an external resistor or device.

An individual transaction is framed by a START condition and a STOP condition. A START condition occurs when a bus master pulls SDA low while the clock is high. A STOP condition occurs when the bus master allows SDA to transition low-to-high when the clock is high. Within the frame, the master has exclusive control of the bus. The UX3328 supports REPEAT START conditions where by the master may simultaneously end one frame and start another without releasing the bus by replacing the STOP condition with a START condition.

Within a frame, the state of SDA may only change when SCL is low. A data bit is transferred on a low-to-high transition of SCL. Data is arranged in packets of 9 bits. The first 8 bits represent data to be transferred (most significant bit first). The last bit is an acknowledge bit. The recipient of the data holds SDA low during the ninth clock cycle of a data packet to acknowledge (ACK) the byte. Leaving SDA to float high on the ninth bit signals a not-acknowledged (NACK) condition. The interpretation of the acknowledge bit by the sender will depend on the type of transaction and the nature of the byte being received.

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6.2 Device Addressing

Clock and Data Transitions: The SDA pin is normally pulled high with an external

resistor or device. Data on the SDA pin may only change during SCL-low time periods. Data changes during SCL-high periods will indicate a START or STOP condition depending on the conditions discussed below.

START Condition: A high-to-low transition of SDA with SCL high is a START condition that must precede any other command.

STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition. Acknowledge: All address and data bytes are transmitted through a serial protocol. The UX3328 pulls the SDA line low during the ninth clock pulse to acknowledge that it has received each word.

The first byte to be sent after a START condition is an address byte. The first seven bits of the byte contain the target slave address (msb first). The eighth bit indicates the transaction type – „0‟= write, „1‟ = read. Each slave interface on the bus is assigned a 7-bit slave address. If no slave matches the address broadcast by the master then SDA will be left to float high during the acknowledge bit and the master receives a NACK. The master must then assert a STOP condition. If a slave identifies the address then it acknowledges the master and proceeds with the transaction identified by the type bit.

Figure 18. address decoding example – slave not addressing

6.3 Write Transaction

Figure 19 shows an example of a write transaction. The address byte is successfully acknowledged by the slave, and the type bit is set low to signify a write transaction. After acknowledge the master sends a single data byte. All signal is controlled by the master except for the SDA line during the acknowledge bits. During acknowledge the direction of the SDA line is reversed and the slave pulls SDA low to return a „0‟ (ACK) to the master.

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

Figure 19. Write transaction

If the slave is unable to receive data then it should return a NACK after the data byte. This

will cause the master to issue a STOP and thus terminate the transaction.

The UX3328 interprets the first data byte as a register address. This will be used to set an internal memory pointer. Subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer. The pointer is auto-incremented after each byte. There is no limit to the number of bytes which may be written in a single burst to the internal RAM of the UX3328. If, however, the write access is destined for the EEPROM the requirements of page writes specified for the EEPROM apply.

If the slave is not ready to receive a byte then it may hold SCL low immediately after the acknowledge bit. When SCL is released the master starts to send the next byte. This is known as clock stretching. The UX3328 slave interface will not clock stretch at up to 400 kHz SCL frequency.

6.4 Read Transaction

Figure 20. Read transaction

Figure 20 shows an example of a 2 byte read transaction. The address byte is successfully acknowledged by the slave, and the type bit is set high to signify a read. After the ACK the slave returns a byte from the location identified by the internal memory pointer. This pointer is then auto-incremented. The slave then releases SDA so that the master can ACK the byte. If the slave receives an ACK then it will send another byte. The master identifies the last byte by sending a NACK to the slave. The master then issues a STOP to terminate the transaction.

Thus, to implement a random access read transaction, a write must first be issued by the master containing a slave address byte and a single data byte (the register address) as

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

shown in Figure 18. This sets up the memory pointer. A read is then sent to retrieve data

from this address (see Figure 20).

7 Register Map

Where a single power-on reset (PoR) value is shown for a range of addresses, that value applies to all bytes in the range. Note that the power on reset values may be overwritten during initialization from the EEPROM.

For registers containing a single 8-bit field, the most significant bit of the field is stored in bit 7 of the register byte.

R Bit is read only. A write to this bit via the TWI will have no effect. The value may be changed by the device itself as part of its normal operation.

R/W Bit is readable and writable via the TWI. The value will not be changed by the device itself except under a device reset. Password permission Permission A B C D E F G H I

Digital diagnostics register: Addr(Hex) 00-01 02-03 04-05 06-07 08-09 0A-0B 0C-0D

Read All All PW2 All PW1 all NA NA NA Write PW2 NA PW2 All PW1 PW1 all PW2 NA Bytes Name 2 2 2 2 2 2 2 Temp High alarm Temp Low alarm Temp High warning Temp Low warning Voltage High alarm Voltage Low alarm Voltage High warning Access Description A A A A A A A See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-37 38-3B 3C-3F 40-43 44-47 48-4B 4C-4D 4E-4F 50-51 52-53 -55 56-57 58-59 5A-5B 5C-5E 5F 60-61 62-63 -65 66-67 68-69 6A-6D 6E 6F

2 2 2 2 2 2 2 2 2 2 2 2 2 16 4 4 4 4 4 2 2 2 2 2 2 2 2 3 1 2 2 2 2 2 4 1 1 Voltage Low warning Bias High alarm Bias Low alarm Bias High warning Bias Low warning TX Power High alarm TX Power Low alarm TX Power High warning TX Power Low warning RX Power High alarm RX Power Low alarm RX Power High warning RX Power Low warning reserved Rx_PWR(4) Rx_PWR(3) Rx_PWR(2) Rx_PWR(1) Rx_PWR(0) Tx_I(Slope) Tx_I(Offset) Tx_PWR(Slope) Tx_PWR(Offset) T (Slope) T(Offset) V(Slope) V(Offset) Reserved Checksum Temperature VCC Tx Bias TX Power RX Power Reserved Optional Status/Control bits Reserved A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 70-71 72-73 74-75 76-77 78-7A 7B-7E 7F 2 2 2 2 3 4 1 Alarm flags Reserved Warning flags Reserved Vendor Specific PWE Table_select A A A A A G D See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification See SFF 8472 specification Password entry Select table of registers mapped to addresses 80h to FFh Table 00/01h: Addr(hex) 80-F7 F8-FF Table 03h: Addr(hex) 80 81 82 83 84 85 86 87 88 8A 8B 8C 8D 8E-8F 90-91 92-93 Bytes Name 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 EEPROMIdenfier0 TX_CRTL0 TX_CTRL1 TX_CTRL2 BiasMax Iapcset TX_CTRL3 Biaspre Imodc TX_CTRL4 TX_CTRL5 TEMP_RX_CTRL RXAlarmDAC RX_CTRL TEMP_SLOPE TEMP_OFFSET VCC_SLOPE Access Description C C C C C C C C C C C C C C C C C Pro number/ load check Control bits for TX Control bits for TX Control bits for TX Set LDD maximum bias current in close loop Set the destination current of apc circuit Control bits for Tx Set the constant bias current Set the constant mod current Control bits for TX Control bits for TX Control bits for RX The DAC output of RX alarm Control bits for RX Slope for temperature internal calibration Offset for temperature internal calibration Slope for voltage internal calibration Bytes Name 120 8 User EEPROM Vendor Specific Access Description D/E D/E See SFF 8472 specification See SFF 8472 specification

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 94-95 96-97 98-99 9A-9B 9C-9D 9E-9F A0-A1 A2-A3 A4-A5 A6-A7 A8-A9 AA-AB AC-AD AE-AF B0 B1 B2 B3-B6 B7-BA BB BC BD BE BF 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 4 4 1 1 1 1 1 VCC_OFFSET BIAS_SLOPE BIAS_OFFSET TX_SLOPE TX_OFFSET RX_SLOPE2 RX_OFFSET2 RX_SLOPE1 RX_OFFSET1 RX_SLOPE0 RX_OFFSET0 RX_COMP1 RX_COMP0 INTER_TEST6 APD_DACC SLAVE_ADDRESS DDM_CTRL PW1 PW2 SECURITY_SEL BIASCT_R LDD_FAULT RX_STATUS INIT_STATE C C C C C C C C C C C C C C C C C C C C B B B B offset for voltage internal calibration Slope for bias current internal calibration Offset for bias current internal calibration Slope for TX power internal calibration Offset for TX power internal calibration Slope2 for RX power internal calibration Offset2 for RX power internal calibration Slope1 for RX power internal calibration Offset1 for RX power internal calibration Slope0 for RX power internal calibration Offset0 for RX power internal calibration Preset values of turning point of calibration curve Preset values of turning point of calibration curve - Set the constant APD current Control bits for DDM function Password one Password two Set the current security level of registers the status of the bias counter The status of the conditions for generating TX fault signal The status of RX power Indicate the initialization Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications status after power up C0 C1 C2 C3 C4 C5 C6 C7 C8-C9 CA CB CC-FF Table 04h: Addr(hex) 80-BB BC-FF Table 05h: Addr(hex) 80-BB BC-FF Table 06h: Addr(hex) 80-BB BC-FF Bytes Name 60 68 APD TLUT UNDEFINED Access Description C I UNDEFINED Bytes Name 60 68 MOD TLUT UNDEFINED Access Description C I MOD current vs temperature look-up table UNDEFINED Bytes Name 60 68 BIAS TLUT UNDEFINED Access Description C I BIAS current vs temperature look-up table UNDEFINED 1 1 1 1 1 1 1 1 2 1 1 52 SYS_STATUS EEPROM_FLAG BIASLUT IMOD DEBUG_DATA APD_DAC TEMP_DATA EEPROM_FAIL RX_ADC_VALUE EEPROMchksum EEPROMIdenfier1 UNDEFINED B B B B B B B B B C C I indicate The current security level The status of the operation of eeprom The Tlut Bias current The Tlut MOD current - The Tlut APD current the ADC value of the sampled temperature The flags of eeprom the ADC value of the sampled RX POWER Checksum Pro number/ load check - Register details: 6Eh Bit 7 STA_CTRL Field name TX Disable Type R/W Por 0 Optional status/control bits Digital state of the TX Disable Input Pin. Updated Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications State 6 Soft TX Disable R/W 0 within 100msec of change on pin. Read/write bit that allows software disable of laser. Writing „1‟ disables laser. Turn on/off time is 100 msec max from acknowledgement of serial byte transmission. This bit is „OR‟d with the hard TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default enabled unless pulled low by hardware. If Soft TX Disable is not implemented, the transceiver ignores the value of this bit. Default power up value is 0. Reserved Digital state of the SFP RX Rate Select Input Pin. Updated within 100msec of change on pin. Read/write bit that allows software RX rate select. Writing „1‟ selects full bandwidth operation. This bit is “OR‟d with the hard RX RATE_SELECT pin value. Enable/disable time is 100msec max from acknowledgement of serial byte transmission. Soft RX rate select does not meet the autonegotiation requirements specified in FC-FS. Default at power up is zero. If Soft RX Rate Select is not implemented, the transceiver ignores the value of this bit. Digital state of the TX Fault Output Pin. Updated within 100msec of change on pin. Digital state of the LOS Output Pin. Updated within 100msec of change on pin. Indicates transceiver has achieved power up and data is ready. Bit remains high until data is ready to be read at which time the device sets the bit low. 5 4 3 - R/W 0 0 0 RX Rate Select R/W State Soft RX Rate R/W Select 2 1 0 LtchFt_R LOS R/W R/W 0 0 1 Data_Ready_BaR/W r 7B-7Eh PWE Type 7Fh

R/W Por Controls read/write access to registers. Level 1 FFh access when PWE = PW1. Level 2 access when PWE = PW2. TABLE_SELECT Por 00h Indicate the map address for register tables. Type R/W Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 80h 81h Bit 7 6 5 EEPROMIdenfier0 Por AAh Pro number/ load check Type R/W TX_CTRL0 Field name APCSCALE(2) APCSCALE(1) APCSCALE(0) The register indicates the control bits for TX POWER. Type R/W R/W R/W Por 0 0 0 Select APC scales down level for Iapcset and Imod 000: ×1 001: ×0.8 010: ×0.667 011: ×0.5 100: ×0.4 101: ×0.33 110: ×0.287 111: ×0.25 set the compare level of TX_SD current 00:1/8 of Iapcset 01:2/8 of Iapcset 10:3/8 of Iapcset 11:4/8 of Iapcset set the input range of apc hysteresis comparator 00: 2LSB 01: 4LSB 10: 8LSB 11: 16LSB Apc start control bit 1: enable 0: disable 4 3 Txsdset(1) Txsdset(0) R/W R/W 0 0 2 1 Apcrange(1) Apcrange(0) R/W R/W 0 0 0 Starten R/W 0 82h Bit 7 TX_CTRL1 Field name Lpow Type R/W The register indicates the control bits for TX Por POWER. 0 Tx power control bit 0: normal 1: low power The timing constant of TX_SD 0:60ns, 1:200ns Set Bias LUT enable signal 0: disable 1: enable 6 SD_C 5 Bsluten R/W 0

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 4 CL_OLn R/W 0 Select the close/open loop mode 1: close loop 0: open loop Set MOD LUT enable signal 0: disable 1: enable Select the polarity of the signal channel 0: in-phase 1: reverse Set the disable function while Fault 0: enable 1: disable Set the frequence of the fast apc clock 0: 10MHz 1: 5MHz 3 ModLutEn R/W 0 2 Inpolsw R/W 0 1 Ftshdnen R/W 0 0 Fstclk1_2 R/W 0 83h Bit 7 TX_CTRL2 Field name Apcfsst Type R/W The register indicates the control bits for TX Por POWER. 0 set the function of the fast apc 0: disable 1: enable Set the largest current of MD 00: ×4 level, 50uA 01: ×1 level, 200uA 10: ×1/4 level, 800uA 11: ×1/16 level, 3.2mA Set duty-cycle distortion of eyediagram 6 5 MDM(1) MDM(0) R/W R/W 0 0 4 3 2 1 0 84h 85h

Vdcdc(4) Vdcdc(3) Vdcdc(2) Vdcdc(1) Vdcdc(0) R/W R/W R/W R/W R/W 0 0 0 0 0 Biasmax Por 00h Set LDD maximum bias current in close loop Type R/W Iapcset Type R/W Por Set the destination current of apc circuit with 00h 83(6-5)h Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 86h Bit 7 TX_CTRL3 Field name Bsmaxprotect Type R/W The register indicates the control bits for TX Por POWER. 0 the protection function of bias over-current 0: disable 1: enable Set the time constant of slow apc circuit 00: 5us; 01: 15us; 10: 30us; 11: 60us; Imod compensation factor set 00000: no compensation; 11111: maximum compensation. 6 5 MDC(1) MDC(0) R/W R/W 0 0 4 3 2 1 0 87h 88h h Bit 7 6 5 4 3 2 Imt(4) Imt(3) Imt(2) Imt(1) Imt(0) Biaspre R/W R/W R/W R/W R/W 0 0 0 0 0 Set the constant bias current Por 00h Set the constant mod current Por 00h The register indicates the control bits for TX Por POWER. 0 0 0 0 0 0 Select the polarity of the BEN signal 0: in-phase Only for internal use, must be set to „0‟. Only for internal use, must be set to „1001‟. Type R/W Imodc Type R/W TX _CTRL4 Field name TX_TEST1 Type R/W TX_TEST2 (3) R/W TX_TEST2 (2) R/W TX_TEST2 (1) R/W TX_TEST2 (0) R/W BEN_pch R/W 1: reverse 1 CMOS_SEL R/W 0 TX SD output voltage level 0: TTL 1: CMOS Set APD LUT enable signal 0: enable 1: disable 0 APD_CTRL R/W 0

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 8Ah Bit 7 6 5 4 3 TX_CTRL5 Field name FaultSet(4) FaultSet(3) FaultSet(2) FaultSet(1) FaultSet(0) Type R/W R/W R/W The register indicates the control bits for TX Por POWER. 0 0 0 0 0 Set the qualifications of TX FAULT 0: disable 1: enable FaultSet[0]: VDD>3.9V or VDD<2.7V FaultSet[1]: RREF floating, short to ground or short to VDD FaultSet[2]: LDOP or LDON short to ground FaultSet[3]: BIASP or BIASN short to ground FaultSet[4]: BIAS > or = BIASMAX Only for internal use, must be set to „1‟. Only for internal use, must be set to „0‟. Set the DA current output direction 0: source 1: sink Control bits for RX 2 1 0 TX_TEST3 TX_TEST4 DAI_PNS R/W R/W R/W 0 0 0 8Bh Bit 7 TEMP_RX_CTRL Field name DA_LPOW Type R/W Por 0 DA power control bit 0: normal 1: low power Only for internal use, must be set to „1‟. Only for internal use, must be set to „0‟. Only for internal use, must be set to „0‟. Select the polarity of los output 0: the alarm of LOSP output(if alarm is high, de-alaram is low) 1: the alarm of LOSN output(if alarm is low, de-alarm is high) LA output set in los state 0: enable auto Squelch function(keep the level of common-mode signal) 1: disable auto squelch function LA los function input select 0: VGA; 1: TIA monitor and VGA in the biggest gain LA los hysteresis select 0: 2dB; 6 5 4 3 TX_TEST5 TX_TEST6 TX_TEST7 Lopol R/W R/W R/W R/W 0 0 0 0 2 Squ R/W 0 1 Losel R/W 0 0

hysel R/W 0 Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 1: 3dB 8Ch 8Dh Bit 7 RX_CTRL Field name Rx_limscope Type R/W Por 0 Restriction scope, 0: 300mVpp, 1: 400mVpp Bandwidth optimize 00: 2.5Gbps; 01: 1.25Gbps; 10:622Mbps; 11:155Mbps; The polarity of the LA signal channel 0: Synchronism output; 1: Inverted output LA irop control bit, the input resistor of irop will be set by 0: auto control 1: set by 8D(2-1)h Set the input level of LA monitor current 00: 80uA~1mA(-10~0dBm) 01: 10uA~112uA(-20~-8dBm) 10: 1.2uA~15uA(-30~-18dBm) 11: 0.1uA~1.9 uA(-38~-28dBm) LA power control 0: normal 1: standby Slope for temperature internal calibration Por 0000h offset for temperature internal calibration Por 0000h Control bits for Rx RxAlarmDAC Por 00h The DAC output of RX alarm Type R/W 6 5 Bwd(1) Bwd(0) R/W R/W 0 0 4 Dapol R/W 0 3 Ctrl_rssi R/W 0 2 1 Irop(1) Irop(0) R/W R/W 0 0 0 std R/W 0 8E-8Fh TEMP_SLOPE Type 90-91h TEMP_OFFSET Type 92-93h VCC_SLOPE

R/W R/W Slope for supply voltage internal calibration Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications Type R/W Por 0000h offset for supply voltage internal calibration 94-95h VCC_OFFSET Type 96-97h BIAS_SLOPE Type 98-99h BIAS_OFFSET Type 9A-9Bh Tx_SLOPE Type 9C-9Dh Tx_OFFSET Type 9E-9Fh Rx_SLOPE2 Type A0-A1h Rx_OFFSET2 Type A2-A3h Rx_SLOPE1 Type A4-A5h Rx_OFFSET1 Type A6-A7h Rx_SLOPE0 Type A8-A9h Rx_OFFSET0 Type AA-ABh RX_COMP1 Type R/W Por R/W Por 0000h R/W Por 0000h R/W Por 0000h R/W Por 0000h R/W Por 0000h R/W Por 0000h R/W Por R/W Por 0000h R/W Por 0000h R/W Por 0000h R/W Por 0000h Slope for bias current internal calibration offset for bias current internal calibration Slope for transmitted power internal calibration offeset for transmitted power internal 0000h calibration Slope2 for received power internal calibration Offset2 for received power internal calibration Slope1 for received power internal calibration Offset1 for received power internal calibration Slope0 for received power internal calibration Offset0 for received power internal calibration Preset values of turning point of calibration 0000h curve between Rx_SLOPE2 and Rx_SLOPE 1 (Rx_OFFSET 2 and Rx_OFFSET 1)

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

AC-ADh RX_COMP0 Type AE-AFh INTER_TEST Type B0h B1h SLVAE_ADDRESS Por Type R/W The two-wire serial slave interface address. The A2h two least significant bits will be saved as zeros. The saved address is thus a new A0h address.A2h is always slaveaddress+2 Control bits for DDM function Type R/W R/W R/W Por 0 0 0 Internal calibration, write „1‟ is set External calibration, write „1‟ is set Debug mode enable signal 0: normal 1: debug mode Pin20 output select 0: TX_SD: 1: AMUX Amux address for debug mode 0000, temperature 0001, VDD/3 0010, BIAS 0011, MD 0100, ROP 0101, CF voltage 0110, NC 0111, Vmod_mon 1000, NC 1001, Vapch_mon 1010, Resistor test APD_DACC Por 00h Set the constant APD current Type R/W R/W Por 0000h Only for internal use, must be set to „0000h‟. R/W Por Preset values of turning point of calibration 0000h curve between Rx_SLOPE 1 and Rx_SLOPE 0 (Rx_OFFSET 1 and Rx_OFFSET 1) B2h DDM_CTRL Bit 7 6 5 Field name IN EXT DEBUG_EN 4 SD_AMUX_C R/W 0 3 2 1 0 AMUX_ADDR(3) AMUX_ADDR(2) AMUX_ADDR(1) AMUX_ADDR(0) R/W R/W R/W R/W 0 0 0 0

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 1011, Vbg_la 1100, NC 1101, NC 1110, NC 1111, NC B3-B6h PW1 Type B7-BAh PW2 Type BB Bit 7 6 5 4 3 Security_sel Field name - - - - A2_TAB0 Type R/W R/W R/W R/W R/W Por 0 0 0 0 0 The most significant four bits are reserved, the least significant four bits set the security level of A0/A2 region Reserved Reserved Reserved Reserved set the security level of table 0 in A2 upper region 1-level 1 0-user level set the security level of A0 upper region 1-level 1 0-user level set the security level of A0 lower region 00/11-user level 01- level one 10 – level two The status of the bias counter Por 00h W Por 00h Level 2 access password W Por 00h Level 1access password 2 A0_UPPER R/W 0 1 0 A0_LOWER(1) R/W A0_LOWER(0) R/W 0 0 BCh BDh LDD_FAULT Bit 7 6 BiasCT_R Type R Field name - - Type R R Por 0 0 The status of the conditions for generating TX fault signal Reserved Reserved Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 5 4 3 2 1 0 - Fault(4) Fault(3) Fault(2) Fault(1) Fault(0) R R R R R R 0 0 0 0 0 0 Reserved Indicate the status of TX FAULT 0: No fault 1:Fault Fault[0]: VDD>3.9V or VDD<2.7V Fault[1]: RREF floating, short to ground or short to VDD Fault[2]: LDOP or LDON short to ground Fault[3]: BIASP or BIASN short to ground Fault[4]: BIAS > or = BIASMAX BEh Rx_status Bit 7 6 5 4 3 2 1 0 Field name - - - - - Type R R R R R Por 0 0 0 0 0 0 0 0 The alarm state of rop circuit: 1- monitor current is too large for current irop level, 0- monitor current is not too large for current irop level. The most significant four bits indicating EEPROM DMA load fail („1‟ = no response from EEPROM during power up), The least significant four bits indicating Data structure corrupt („1‟ = data integrity bytes read from EEPROM during power up are incorrect). Reserved The bit is set to „1‟by the device if the DMA from the A4 region of EEPROM does not complete successfully The bit is set to „1‟ by the device if the DMA from the A2 region of EEPROM does not Reserved Reserved Reserved Reserved Reserved The status of LA ROP current range The status of RX power rop_state(1) R rop_state(0) R Rop_alarm R BFh INIT_STATE Bit Field name Type Por 7 6 - R 0 0 EEPROM_FAIL2 R 5

EEPROM_FAIL1 R 0 Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications complete successfully 4 EEPROM_FAIL0 R 0 The bit is set to „1‟ by the device if the DMA from the A0 region of EEPROM does not complete successfully The bit is set to „1‟ by the device if the data from the A4 region of eeprom fails its integrity check The bit is set to „1‟ by the device if the data from the A2 lower region of eeprom fails its integrity check The bit is set to „1‟ by the device if the data from bytes -94h in A0 region of eeprom fails its integrity check The bit is set to „1‟ by the device if the data from bytes 0-62h in A0 region of eeprom fails its integrity check The register indicate The current security level Type R R R R R R R R Por 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Indicate the current security level for register access. The register indicate Whether the data is written to EEPROM the bit is set to „1‟ by the device if the data of table 6 is not completely written to EEPROM. the bit is set to „1‟ by the device if the data of table 5 is not completely written to EEPROM. the bit is set to „1‟ by the device if the data of table 4 is not completely written to EEPROM. the bit is set to „1‟ by the device if the data of table 3 is not completely written to EEPROM. the bit is set to „1‟ by the device if the data of table 0 is not completely written to EEPROM. 3 2 dsfail3 dsfail2 R R 0 0 1 dsfail1 R 0 0 dsfail0 R 0 C0h SYS_STATUS Bit 7 6 5 4 3 2 1 0 C1h EEPROM_FLAG Bit 7 6 5 4 3

Field name - - - - - - Security(1) Security(0) Field name Type Por 0 0 0 0 0 Eepromflag7 R Eepromflag6 R Eepromflag5 R Eepromflag4 R Eepromflag3 R Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 2 1 0 C2h C3h C4h C5h C6h Eepromflag2 R Eepromflag1 R Eepromflag0 R 0 0 0 the bit is set to „1‟ by the device if the data of A2 lower region is not completely written to EEPROM. the bit is set to „1‟ by the device if the data of A0 upper region is not completely written to EEPROM. the bit is set to „1‟ by the device if the data of A0 lower region is not completely written to EEPROM. biasTlut Por 00h The Tlut BIAS current Type R Imod The Tlut MOD current Por 00h The register is used to store data when UX3328 is in debug mode Indicate the Tlut APD current Por 00h Type R Debug_data Type R APD_DAC Por 00h Type R TEMP_DATA Por 00h Type R Indicate the ADC value of the sampled temperature C7h EEPROM_FAIL_FLAG Bit 7 6 5 4 3 2 Field name Type Por 0 0 0 0 0 0 The register indicate Whether the data is written to EEPROM the bit is set to „1‟ by the device if the data of table 6 written to EEPROM fails to its check. the bit is set to „1‟ by the device if the data of table 5 written to EEPROM fails to its check. the bit is set to „1‟ by the device if the data of table 4 written to EEPROM fails to its check. the bit is set to „1‟ by the device if the data of table 3 written to EEPROM fails to its check. the bit is set to „1‟ by the device if the data of table 0 written to EEPROM fails to its check. the bit is set to „1‟ by the device if the data of A2 lower region written to EEPROM fails to its check. eerxfailflag7 R eerxfailflag6 R eerxfailflag5 R eerxfailflag4 R eerxfailflag3 R eerxfailflag2 R Ver. 2.1 www.uxfastic.com 2011

UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications 1 0 eerxfailflag1 R eerxfailflag0 R 0 0 the bit is set to „1‟ by the device if the data of A0 upper region written to EEPROM fails to its check. the bit is set to „1‟ by the device if the data of A0 lower region written to EEPROM fails to its check. C8-C9h RX_ADC_VALUE Type CAh EEPROMchksum Por Type R/W CBh

EEPROMidentifier1 Por R Por Indicate the ADC value of the sampled RX 0000h POWER 00h Contains the low order 8 bits of the sum of table 4,table 5 ,table 6 and addresses from 80h to B2h of table 3 Pro number/ load check Type R/W 55h 9 Applications Information

Figure 21. Typical application in ONU

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UX3328 Datasheet Chip Multi-functional Integrated Transceiver Single-Chip Solution for FTTX Applications

Figure 21 shows the application of UX3328 in SFF/SFP, and GEPON, GPON systems. The

UX3328 Limiting amplifier is AC-coupled to the TIA in the ROSA. While used in burst mode, DC-coupled is required at the transmitter input and the laser output. In open loop or DDMI function is needed, a monitor photodiode will be required in conjunction with the laser connecting to MD pin.

10 Package Information

UX3328 is packaged in QFN 32 pins 5mm×5 mm.

Figure 22. Package information

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