SBAS275 – DECEMBER 2002
Motor Control Current Shunt
1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator
FEATURES
q16-BIT RESOLUTIONq13-BIT LINEARITY
qRESOLUTION/SPEED TRADE-OFF:
10-Bit Effective Resolution with 20µs SignalDelay (12-bit with 77µs)q±250mV INPUT RANGE WITH SINGLE 5V SUPPLYq2% INTERNAL REFERENCE VOLTAGEq2% GAIN ERROR
qFLEXIBLE SERIAL INTERFACE WITH FOURDIFFERENT MODESqIMPLEMENTED TWINNED BINARY CODING ASSPLIT PHASE OR MANCHESTER CODING FORONE LINE INTERFACINGqOPERATING TEMPERATURE RANGE:
–40°C to +85°C
DESCRIPTION
The ADS1202 is a precision, 80dB dynamic range, delta-sigma (∆∑) modulator operating from a single +5V supply.The differential inputs are ideal for direct connections totransducers or low-level signals. With the appropriate digitalfilter and modulator rate, the device can be used to achieve16-bit Analog-to-Digital (A/D) conversion with no missingcodes. Effective resolution of 12 bits can be maintained witha digital filter bandwidth of 10kHz at a modulator rate of10MHz. The ADS1202 is designed for use in medium reso-lution measurement applications including current measure-ments, smart transmitters, industrial process control, weighscales, chromatography, and portable instrumentation. It isavailable in a TSSOP-8 package.
APPLICATIONS
qMOTOR CONTROL
qCURRENT MEASUREMENTqINDUSTRIAL PROCESS CONTROLqINSTRUMENTATIONqSMART TRANSMITTERSqPORTABLE INSTRUMENTSqWEIGHT SCALES
qPRESSURE TRANSDUCERS
VDDGNDBufferReferenceVoltage2.5VRC Oscillator20MHzInterfaceCircuitM0M1VIN+VIN–2nd-Order∆∑ ModulatorMDATMCLKPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2002, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature (unless otherwise noted)(1)
Supply Voltage, GND to VDD.................................................–0.3V to 6VAnalog Input Voltage Range.........................GND – 0.4V to VDD + 0.3VDigital Input Voltage Range..........................GND – 0.3V to VDD + 0.3VPower Dissipation............................................................................0.25WOperating Virtual Junction Temperature Range, TJ........–40°C to +150°COperating Free-Air Temperature Range, TA....................–40°C to +85°CStorage Temperature Range, TSTG................................–65°C to +150°CLead Temperature 1.6mm (1/16\") from Case for 10s..................+260°CNOTE: (1) Stresses beyond those listed under the Absolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyondthose indicated under the Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
ELECTROSTATICDISCHARGE SENSITIVITYThis integrated circuit can be damaged by ESD. Texas Instru-ments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handlingand installation procedures can cause damage.
ESD damage can range from subtle performance degrada-tion to complete device failure. Precision integrated circuitsmay be more susceptible to damage because very smallparametric changes could cause the device not to meet itspublished specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUMINTEGRALLINEARITYERROR (LSB)12SPECIFIEDMAXIMUMPACKAGETEMPERATUREGAIN ERROR (%)PACKAGE-LEADDESIGNATOR(1)RANGE±2TSSOP-8PW–40°C to +85°CPRODUCTADS1202ADS1202PACKAGEMARKINGADS1202IORDERINGNUMBERADS1202IPWTADS1202IPWRTRANSPORTMEDIA, QUANTITYTape and Reel, 250Tape and Reel, 2000\"\"\"\"\"\"NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
TSSOP
PIN DESCRIPTIONS
PINNUMBER
1234
NAMEMOVIN+VIN–M1GNDMDATMCLKVDD
DESCRIPTIONMode Input
Analog Input: Noninverting InputAnalog Input: Inverting InputMode Input
Power Supply GroundModulator Data Output
Modulator Clock Input or OutputPower Supply, +5V Nominal
M0VIN+VIN–M112ADS1202348765VDDMCLKMDATGND5678
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage, VDD
Analog Input Voltage, VIN
Operating Common-Mode Signal, VCMExternal Clock(1)
Operating Junction Temperature Range
NOTE: (1) With reduced accuracy, minimum clock can go up to 500kHz.
MIN4.75–25008–40
NOM5.0
MAX5.25+250512105
UNITVmVVMHz°C
10
DISSIPATION RATING
TA < 25°CPOWERRATING483.6mWDERATINGFACTORABOVETA = 25°C(1)3.868mW/°CTA = 70°CPOWERRATING309.5mWTA = 85°CPOWERRATING251.4mWEQUIVALENT INPUT CIRCUIT
AVDDRON = 350ΩC(SAMPLE) = 5pFAINDINBVDDPACKAGETSSOP-8NOTE: (1) This is the inverse of the traditional junction-to-ambient thermalresistance (RθJA). Thermal resistances are not production tested and are forinformational purposes only.AGNDDiode Turn on Voltage: 0.35VEquivalent Analog Input CircuitBGNDEquivalent Digital Input Circuit2ADS1202www.ti.comSBAS275ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to +85°C, VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
ADS1202IPWPARAMETERRESOLUTIONDC ACCURACYIntegral NonlinearityDifferential Linearity(1)Input OffsetInput Offset DriftGain ErrorGain Error DriftPower-Supply Rejection RatioANALOG INPUTFull-Scale RangeOperating Common-Mode Signal(2)Input CapacitanceInput Leakage CurrentDifferential Input ResistanceDifferential Input CapacitanceCommon-Mode Rejection Ratio(2)INTERNAL VOLTAGE REFERENCEReference VoltageInitial AccuracyReference Temperature DriftPSRRStartup TimeINLDNLVOSTCVOSGERRTCGERRPSRRFSRCONDITIONSMIN16±30.005±3002±0.252080±120.018±1±10008±2TYP(1)MAXUNITSBitsLSB%LSBµVµV/°C%ppm/°CdBmVVpFnAkΩpFdBdBV%ppm/°CdBmsMHzMHzdBdBdBdB4.75V < VDD < 5.25V+In – (–In)–0.1Common-ModeEquivalent±32053±12859085CMRRAt DCVIN = ±1.25Vp-p at 50kHzScale to 320mVScale to 320mV2.450VOUTdVOUT/dT2.5±20800.12.550±2+-+INTERNAL CLOCK FOR MODES, 0, 1, AND 2Clock FrequencyEXTERNAL CLOCK FOR MODE 3Clock FrequencyAC ACCURACYSignal-to-Noise Ratio + DistortionSignal-to-Noise RatioTotal Harmonic DistortionSpurious Free Dynamic RangeDIGITAL INPUTLogic FamilyHigh-Level Input VoltageLow-Level Input VoltageHigh-Level Input CurrentLow-Level Input CurrentInput CapacitanceDIGITAL OUTPUTHigh-Level Digital OutputLow-Level Digital OutputOutput CapacitanceLoad CapacitancePOWER SUPPLYSupply VoltageOperating Supply CurrentPower DissipationOPERATING TEMPERATURESINADSNRTHDSFDRVIN = ±250mVp-p at 5kHzVIN = ±250mVp-p at 5kHzVIN = ±250mVp-p at 5kHzVIN = ±250mVp-p at 5kHz81610207070.5–8484122467VIHVILIIHIILCJVOHVOLCOCLVDDICCVI = VDDVI = GNDTTL with Schmitt Trigger2.6VDD + 0.3–0.30.80.0052.5–2.50.005.63.90.41.15304.556830405.57.59.537.7.5+85VVµAµApFVVVVpFpFVmAmAmWmW°CVDD = 4.5V, IO = –5mAVDD = 4.5V, IO = –15mAVDD = 4.5V, IO = 5mAVDD = 4.5V, IO = 15mAMode 0Mode 3VDD = 5V, Mode 0VDD = 5V, Mode 3–40NOTES: (1) All typical values are at TA = +25°C. (2) Ensured by design. (3) Integral nonlinearity is defined as one-half the peak-to-peak deviation of the best fitline through the transfer curve for VIN+ = –250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (4) Onlytypical information parameter not tested.
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TIMING DIAGRAMS
tC1MCLKtW1tD1MDATDIAGRAM 1: Mode 0 Operation.
tC2MCLKtW2MDATtD2tD3DIAGRAM 2: Mode 1 Operation.
tC1MCLKtw1tC3MDATtw3101100DIAGRAM 3: Mode 2 Operation.
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TIMING DIAGRAMS (Cont.)
tC4MCLKtw4tD4MDATDIAGRAM 4: Mode 3 Operation.
TIMING CHARACTERISTICS
over recommended operating free-air temperature range –40°C to +85°C, VDD = 5V, and MCLK = 10MHz, unless otherwise noted.
SPECtC1tW1tD1tC2tW2tD2tD3tC3tW3tC4tW4tD4tR1tF1
DESCRIPTIONClock PeriodClock HIGH Time
Data delay after rising edge of clockClock PeriodClock HIGH Time
Data delay after rising edge of clockData delay after falling edge of clockClock PeriodClock HIGH TimeClock PeriodClock HIGH Time
Data delay after falling edge of clockRise Time of ClockFall Time of Clock
MODE00011112233333
MIN
90tC1/2 –5
tC1/4 – 10
180tC2/2 –5tC2/4 – 10tC2/4 – 10
90tC3/2 –510000
MAX110tC1/2 + 5tC1/4 + 10220tC2/2 + 5tC2/4 + 10tC2/4 + 10110tC3/2 + 555tC4 – 10101010
UNITSnsnsnsnsnsnsnsnsnsnsnsnsnsns
NOTE: All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams 1 thru 4.
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TYPICAL CHARACTERISTICS
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 0)210–1INL (LSB)–2–3–4–5–6–7–320
–240
–160–80080160Differential Input Voltage (mV)
240
320
–4
25°C
INL (LSB)210–1
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3)
–40°C
+85°C
25°C
–2–3
+85°C
–40°C
–5–320
–240
–160–80080160Differential Input Voltage (mV)
240320
INTEGRAL NONLINEARITY vs TEMPERATURE
765INL (LSB)43210–40
–20
0
2040Temperature (°C)
60
80
100
Mode 3
Mode 0
0.0100.0090.0080.007INTEGRAL NONLINEARITY vs TEMPERATUREMode 0INL (%)0.0060.0050.0040.0030.0020.0010–40–2002040Temperature (°C)6080100Mode 3OFFSET vs TEMPERATURE3002001000Offset (µV)GAIN vs TEMPERATURE0.14Mode 30.120.10Gain (%)–100–200–300–400–500–600–700–40–2002040Temperature (°C)6080100Mode 0Mode 30.080.060.040.020–40–2002040Temperature (°C)6080100Mode 06
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TYPICAL CHARACTERISTICS (Cont.)
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
RMS NOISE vs INPUT VOLTAGE LEVEL80706071.070.870.670.4SIGNAL-TO-NOISE RATIO vs TEMPERATUREMode 0RMS Noise (µV)403020100–320–240–160–80080160Differential Input Voltage (mV)240320SNR (dB)50Mode 370.270.069.869.669.469.269.0–40–2002040Temperature (°C)6080100SIGNAL-TO-NOISE + DISTORTIONvs TEMPERATURE71.01614Mode 3SINAD (dB)EFFECTIVE NUMBER OF BITSvs DECIMATION RATIO70.6Sinc3 Filter12ENOB70.2Mode 069.8Sinc2 Filter10869.4–40–2002040Temperature (°C)608010004008001200Decimation Ratio (OSR)1600200069.0SPURIOUS-FREE DYNAMIC RANGEAND TOTAL HARMOINIC DISTORTION
vs TEMPERATURE (Mode 0)
959391SFDR (dB)87858381797775–40
–20
0
2040Temperature (°C)
60
80
100
THDSFDR0.5Vp-p5kHz–95–93–91–
SFDR (dB)THD (dB)–87–85–83–81–79–77–75
95939187858381797775–40
SPURIOUS-FREE DYNAMIC RANGEAND TOTAL HARMOINIC DISTORTION
vs TEMPERATURE (Mode 3)
–95–93
SFDR
–91–
THD
THD (dB)–87–85–83–81–79–77–75
–20
0
2040Temperature (°C)
60
80
100
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TYPICAL CHARACTERISTICS (Cont.)
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGEAND TOTAL HARMOINIC DISTORTION
vs INPUT FREQUENCY (Mode 0)
11010090SFDR (dB)80706050
1
Input Frequency (kHz)
10
THD–110–100–90
SFDR (dB)THD (dB)–80–70–60–50
110100
SFDR90
THD80706050
1
Input Frequency (kHz)
10–80–70–60–50–90
THD (dB)SPURIOUS-FREE DYNAMIC RANGEAND TOTAL HARMOINIC DISTORTION
vs INPUT FREQUENCY (Mode 3)
–110–100
SFDROSR = 256Sinc3 FilterOSR = 256Sinc3 FilterFREQUENCY SPECTRUM(4096 Point FFT, fIN = 1kHz, 0.5Vp-p)0Mode 0–20Magnitude (dB)Magnitude (dB)FREQUENCY SPECTRUM(4096 Point FFT, fIN = 5kHz, 0.5Vp-p)0Mode 0–20–40–60–80–100–120–140–40–60–80–100–120–140024681012Frequency (kHz)14161820024681012Frequency (kHz)14161820CLOCK FREQUENCY vs TEMPERATURE10.51009510.29085CMRR (dB)COMMON-MODE REJECTION RATIO vs FREQUENCYMCLK (MHz)9.9807570659.69.360559.0–40–200204060Temperature (°C)8010012050110Frequency of Power Supply (Hz)1008
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TYPICAL CHARACTERISTICS (Cont.)
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
HISTOGRAM OF OUTPUT DATA90200085180080s1600ecne1400)rB75rdu(c1200 cROR70 1000fSo P65re800b60mu600N40055200500100
1k10k100k
432109876159370482Frequency of Power Supply (Hz)
10998876611–––––––––ppm of FSMCLK AND MDATPOWER-SUPPLY CURRENT vs TEMPERATURETYPICAL SINK CURRENT10709605.5V8Mode 0)A7m(50 )LAm6O5VI( Mode 3 tn40tne5errru4.5VruC4C30 tu3ptu202O11000–40–200204060801000123456Temperature (°C)Output Voltage VOL (V)MCLK AND MDATTYPICAL SOURCE CURRENT8070)5.5VAm60( 5VHOI50 tnerr40uC tu30ptuO20104.5V00123456Output Voltage VOH (V)ADS1202
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GENERAL DESCRIPTION
The ADS1202 is a single-channel, 2nd-order, CMOS analogmodulator designed for medium to high resolution conver-sions from DC to 39kHz with an oversampling ratio (OSR) of256. The output of the converter (MDAT) provides a streamof digital ones and zeros. The time average of this serialoutput is proportional to the analog input voltage. The com-bination of an ADS1202 and a Digital Signal Processor(DSP) that is programmed to implement a digital filter resultsin a medium resolution A/D converter system. This systemallows flexibility with the digital filter design and is capable ofA/D conversion results that have a dynamic range thatexceeds 85dB with OSR = 256.
THEORY OF OPERATION
The differential analog input of the ADS1202 is implementedwith a switched capacitor circuit. This switched capacitorcircuit implements a 2nd-order modulator stage, which digi-tizes the input signal into a 1-bit output stream. The sampleclock (MCLK) provides the switched capacitor network andmodulator clock signal for the A/D conversion process, aswell as the output data-framing clock. The clock source canbe internal as well as external. Different frequencies for thisclock allow for a variety of solutions and signal bandwidths(however, this can only be utilized in mode 3). The analoginput signal is continuously sampled by the modulator andcompared to an internal voltage reference. A digital stream,which accurately represents the analog input voltage overtime, appears at the output of the converter.
+5V+5VVDDODSPM27Ω10nFM0VIN+VIN–27Ω0.1µF0.1µFM1ADS1202VDDMCLKMDATGND0.1µFSPICLKSPISIMOVSSOFIGURE 1. Connection Diagram for the ADS1202 Delta-Sigma Modulator Including DSP.
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ANALOG INPUT STAGEAnalog Input
The input design topology of the ADS1202 is based on a fullydifferential switched-capacitor architecture. This input stageprovides the mechanism to achieve low system noise, highcommon-mode rejection (90dB), and excellent power-supplyrejection. The input impedance of the analog input is depen-dant on the input capacitor and modulator clock frequency(MCLK), which is also the sampling frequency of the modu-lator. Figure 2 shows the basic input structure of the ADS1202.The relationship between the input impedance of the ADS1202and the modulator clock frequency is:
AIN(Ω)=
1012
7•fMCLK(MHz)
(1)
the linearity of the device is ensured only when the analogvoltage applied to either input resides within the range definedby –320mV and +320mV.
Modulator
The modulator sampling frequency (CLK) can be operatedover a range of a few MHz to 12MHz in mode 3. Thefrequency of MCLK can be decreased to adjust for the clockrequirements of the application. The external MCLK musthave double the modulator frequency.
The modulator topology is fundamentally a 2nd-order, charge-balancing A/D converter, as the one conceptualized in Figure 3.The analog input voltage and the output of the 1-bit Digital-to-Analog Converter (DAC) are differentiated, providing an analogvoltage at X2 and X3. The voltage at X2 and X3 are presentedto their individual integrators. The output of these integratorsprogress in a negative or positive direction. When the value ofthe signal at X4 equals the comparator reference voltage, theoutput of the comparator switches from negative to positive, orpositive to negative, depending on its original state. When theoutput value of the comparator switches from HIGH to LOW orvice versa, the 1-bit DAC responds on the next clock pulse bychanging its analog output voltage at X6, causing the integratorsto progress in the opposite direction. The feedback of themodulator to the front end of the integrators forces the value ofthe integrator output to track the average of the input.The input impedance becomes a consideration in designswhere the source impedance of the input signal is HIGH. Inthis case, it is possible for a portion of the signal to be lostacross this external source impedance. The importance of thiseffect depends on the desired system performance. There aretwo restrictions on the analog input signal to the ADS1202.Under no conditions should the current into or out of theanalog inputs exceed 10mA. The absolute input voltage rangemust stay in the range GND – 0.4V to VDD + 0.3V. If either ofthe inputs exceed these limits, the input protection diodes onthe front end of the converter will begin to turn on. In addition,
RSW350kΩ (typ)AIN+1.5pFCINT7pF (typ)VCMHighImpedance> 1GΩSwitching Frequency= CLK1.5pFRSW350kΩ (typ)AIN–CINT7pF (typ)HighImpedance> 1GΩFIGURE 2. Input Impedance of the ADS1202.
fCLKX2X3X4DATAVREFComparatorX(t)fSIntegrator 1Integrator 2X6D/A ConverterFIGURE 3. Block Diagram of the 2nd-Order Modulator.
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DIGITAL OUTPUT
The timing diagram for the ADS1202 data retrieval is shownin the Timing Diagrams. When an external clock is applied toMCLK, it is used as a system clock by the ADS1202, as wellas a framing clock for data out (this procedure, however, canonly be utilized in mode 3). The modulator output data, whichis a serial stream, is available on the MDAT pin. Typically,MDAT is read on the falling edge of MCLK.
An input differential signal of 0V will ideally produce a streamof ones and zeros that are HIGH 50% of the time and LOW50% of the time. A differential input of 256mV will produce astream of ones and zeros that are HIGH 80% of the time. Adifferential input of –256mV will produce a stream of onesand zeros that are HIGH 20% of the time. The input voltageversus the output modulator signal is shown in Figure 4.
ods can be used to obtain this synchronization. The firstmethod has the delta-sigma modulator and the filter receivethe clock signal from the master clock. The second methodhas the delta-sigma modulator transmit the clock signaltogether with the data signal. The third method has the filterderivate the clock signal from the received waveform itself.An ideal solution is a delta-sigma modulator with a flexibleinterface, such as the ADS1202, which can provide flexibleoutput format on the output lines MCLK and MDAT, thuscovering different modes of operation. The signal type thatcan be provided is selected with control signals M0 and M1.
FLEXIBLE DELTA-SIGMA INTERFACE
Figure 5 illustrates the flexible interface of the ADS1202delta-sigma converter. The control signals M0 and M1 areentered in the decoder that decodes the input code andselects the desired mode of operation. Five output signalsfrom the decoder control the RC oscillator, multiplexer MUX1,multiplexer MUX2, multiplexer MUX3, and multiplexer MUX4.MUX1 is controlled by the decoder signal. When the internalRC oscillator is used, the control signal from the decoderenables the RC oscillator. At the same time, MUX1 uses theINTCLK signal as a source for the output signal from MUX1,which is entering the code generator. If the external clock isused, the control signal from the decoder disables the inter-nal RC oscillator and the control signal from the decoder, andpositions MUX1 so that EXTCLK provides the output signalfrom MUX1 as the input in the code generator.
MUX2 selects the output clock, OCLK. The control signalcoming from the decoder controls the output clock. Twosignals come from the code generator as a half clock fre-quency, CLK/2, and as a quarter clock frequency, CLK/4,and provide MUX2 with the input signal. The control signalwill select two different output modes on the OCLK signal ashalf clock or quarter clock.
DIGITAL INTERFACE
INTRODUCTION
The analog signal that is connected to the input of the delta-sigmamodulator is converted using the clock signal (CLK) applied to themodulator. The result of the conversion, or modulation, is theoutput signal DATA from the delta-sigma modulator.
In most applications where direct connection is realizedbetween delta-sigma modulator and DSP or uC, two stan-dard signals are provided. The MDAT and MCLK signalsprovide the easiest means of connection. If it is required toreduce the number of connection lines, having two signals issometimes not an optimal solution.
The receiver, DSP, or other control circuit must sample theoutput data signal from the modulator at the precise samplinginstant. To do this, sampling a clock signal at the receiver isneeded in order to synchronize with the clock signal at thetransmitter. The delta-sigma modulator clock signal, receiver,filter, and clock must be synchronized. Three general meth-
Modulator Output+FS (Analog Input)–FS (Analog Input)Analog InputFIGURE 4. Analog Input Versus Modulator Output of the ADS1201.
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Interface CircuitM0DecoderM1RCOscillatorINTCLKEXTCLKMUX1MUX4MCLKOCLKCodeGeneratorMUX2CLK/2CLK/4MUX3MDATCLKDATAAIN∆∑ModulatorFIGURE 5. Flexible Interface Block Diagram.
The code generator receives the clock signal from MUX1 andgenerates the delta-sigma modulator clock (CLK) divided ashalf clock (CLK/2) and quarter clock (CLK/4). At the sametime, the continuous data stream (DATA) coming from thedelta-sigma modulator is elaborated by the Code Generator.Twinned binary coding (also known as split phase or Manches-ter coding) is implemented and then output from the codegenerator to MUX3.MUX3 selects the source of the output bit stream data,MDAT. The control signal coming from the decoder controlsthe input source of MDAT. Two signals are coming in to theMUX3, one directly from the delta-sigma modulator and theother from the code generator. The control signal from thedecoder can select two different output modes on the signalMDAT: bit stream from a delta-sigma modulator or twinnedbinary coding of the same signal.
The last control signal from the decoder controls MUX4.MUX2 selects the input or output clock, the MCLK signal.The control signal coming from the decoder controls thedirection of the clock. One signal entering MUX4 from MUX2comes as a clock signal OCLK. Another signal leaves MUX4and provides an input to MUX1 as an external clock, EXTCLK.
The control signal from the decoder can select two differentmodes on MCLK, one as an output of the internal clock signaland another as the input for the external clock signal.As a function of two control signals (M0 and M1), the decodercircuit, using five control signals, will set multiplexers in orderto obtain the desired mode of operation.
DIFFERENT MODES OF OPERATION
Figure 5 presents mode selectors (input signals M0 and M1)that enter the flexible interface circuit and decoder thatdecodes the input code, and select the desired mode ofoperation. With two control lines it is possible to select fourdifferent modes of operation mode 0, mode 1, mode 2, andmode 3, which are shown in Table I.
MODE0123
DEFINITION
Internal Clock, Synchronous Data OutputInternal Clock, Synchronous Data Output,Half Output Clock Frequency
External Clock, Synchronous Data Output
M1LOWLOW
MOLOWHIGHLOWHIGH
Internal Clock, Manchester Coded Data OutputHIGH
HIGH
TABLE I. Mode Definition and Description.
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Mode 0
In mode 0 both input signals, M0 and M1, are LOW. Thecontrol signal coming from the decoder enables the internalRC oscillator that provides the clock signal INTCLK as aninput to MUX1. The control signal coming from the decoderalso positions MUX1 so that the output signal, which is aninput signal for the code generator, is INTCLK. Anothercontrol signal from the decoder circuit positions MUX3 sothat the source for the output signal MDAT is the signalarriving directly from the delta-sigma modulator, DATA. MUX2is positioned for the mode controlled by the signal comingfrom the decoder so output signal OCLK is CLK/2. The signaltimings for mode 0 operation are presented in Figure 6. Inthis mode, DSP or µC read MDAT data on every rising edgeof the MCLK output clock.
Mode 1
In mode 1, the input signal M0 is HIGH and M1 is LOW (seeTable I). The first control signal coming from the decoderenables the internal RC oscillator that provides clock signalINTCLK as an input to MUX1. The second control signalcoming from the decoder positions MUX1 so that the outputsignal that is the input signal to the code generator isINTCLK. The output signal from the delta-sigma modulator,DATA, is also the MDAT signal coming from the modulatorbecause the control signal from the decoder positions MUX3for that operation. MUX2 is positioned for the mode con-trolled by the control signal coming from the decoder with anOCLK of CLK/2. Output clock signal MCLK comes throughMUX4 from MUX2 as OCLK or CLK/2. The signal timings formode 1 operation are presented in Figure 7. In this mode,DSP or µC read data on every edge, rising and falling, of theoutput clock.
CLKDATAMCLKMDATFIGURE 6. Signal Timing in Mode 0.
CLK DATAMCLKMDATFIGURE 7. Signal Timing in Mode 1.
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Mode 2
In mode 2, M0 is low and M1 is HIGH (see Table I). The controlsignal coming from the decoder enables the internal RC oscil-lator that provides the clock signal INTCLK as an input to MUX1.Another control signal coming from the decoder positions MUX1so that the output signal that is the input signal to the codegenerator is INTCLK. The output signal MDAT comes from thecode generator because the control signal from the decoderpositions MUX3 for that operation. The DATA signal comingfrom the delta-sigma modulator enters the code generator,where it combines with the clock signal, and twinned binarycoding is implemented as split phase or Manchester coding,providing the output signal for MUX3. The MCLK output clockis not active, as multiplexers MUX2 and MUX4 are positionedfor this mode controlled by the control signals coming from thedecoder. The signals timings for mode 2 operation are pre-sented in Figure 8. In this mode, DSP or µC need to derive theclock signal from the received waveform itself. Different clockrecovery networks can be implemented.
Mode 3
mode 3 is similar to mode 0; the only difference is that anexternal clock (EXTCLK) is provided. In mode 3, both inputsignals M0 and M1 are HIGH (see Table I). The controlsignal coming from the decoder disables the internal RCoscillator. The input signal EXTCLK provides the clocksignal as an input to MUX1. The control signal coming fromthe decoder positions MUX1 so that the output signal thatis the input signal to the code generator is EXTCLK. Theoutput signal MDAT is the DATA signal coming directly fromthe delta-sigma modulator because the control signal fromthe decoder positions MUX3 for that operation. The signaltimings for mode 3 operation are presented in Figure 9. Inthis mode, DSP or µC read data on every falling edge of theinput clock.
CLK DATAMCLKMDATFIGURE 8. Signal Timing in Mode 2.
MCLKCLKDATAMDATFIGURE 9. Signal Timing in Mode 3.
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APPLICATIONS
Mode 0 operation in a typical application is shown in Figure10. Measurement of the motor phase current is done via theshunt resistor. For better performance, both signals arefiltered. R2 and C2 filter noise on the noninverting inputsignal, R3 and C3 filter noise on the inverting input signal, andC4 in combination with R2 and R3 filter the common-modeinput noise. In this configuration, the shunt resistor is con-nected via three wires with the ADS1202.
The power supply is taken from the upper gate driver powersupply. A decoupling capacitor of 0.1µF is recommended forfiltering the power supply. If better filtering is required, anadditional 1µF to 10µF capacitor can be added.
The control lines M0 and M1 are both LOW while the part isoperating in mode 0. Two output signals, MCLK and MDAT,are connected directly to the optocoupler. The optocouplercan be connected to transfer a direct or inverse signalbecause the output stage has the capacity to source and sinkthe same current. The discharge resistor is not needed inparallel with optocoupler diodes because the output driverhas the capacity to keep the LED diode out of the charge.
The DSP can be directly connected at the output of twochannels of the optocoupler, C28x or C24x. In this configu-ration, the signals arriving at C28x or C24x are standarddelta-sigma modulator signals and are connected directly tothe SPICLK and SPISIMO pins. Being a delta-sigma con-verter, there is no need to have word synch on the serialdata, so SPI is ideal for connection. McBSP would work aswell in SPI mode.
When component reduction is necessary, the ADS1202 canoperate in mode 2, as shown in Figure 11. M1 is HIGH andM0 is LOW. Only the noninverting input signal is filtered.R2 and C2 filter noise on the input signal. The inverting inputis directly connected to the GND pin, which is simultaneouslyconnected to the shunt resistor.
The output signal from the ADS1202 is Manchester coded. Inthis case, only one signal is transmitted. For that reason, oneoptocoupler channel is used instead of two channels, as inthe previous example of Figure 10. Another advantage of thisconfiguration is that the DSP will use only one line perchannel instead of two. That permits the use of smaller DSPpackages in the application.
HV+FloatingPower SupplyGatedDrive CircuitR1R227ΩD15.1VC10.1µF C410nF ADS1202M0VIN+VIN–VDDMCLKMDATGNDR4R5OptocouplerC28xorC24xSPICLKRSENSER327ΩC20.1µF C30.1µF M1SPISIMOPowerSupplyGated Drive CircuitHV–FIGURE 10. Application Diagram in Mode 0.
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HV+FloatingPower SupplyGatedDrive CircuitR1R227ΩD15.1VC10.1µF ADS1202M0VIN+VDDMCLKMDATGNDR4OptocouplerC28xorC24xRSENSEPowerSupplyC20.1µF VIN–M1Gated Drive CircuitHV–FIGURE 11. Application Diagram in Mode 2.
HV+FloatingPower SupplyGate DriveCircuitC28xorC24xCVDDADS1202C10.1µF SPICLKSPISIMOR227Ω+RSENSE–M0VIN+C20.1µF VIN–M1VDDMCLKMDATGNDDVDDFIGURE 12. Application Diagram without Galvanical Isolation in Mode 0.
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R127Ω+RSENSE–C10.1µFADS1202M0VIN+VIN–M1VDDMCLKMDATGNDC40.1µFR227Ω+RSENSE–C20.1µFADS1202M0VIN+VIN–M1VDDMCLKMDATGNDC50.1µFC28xorC24xCVDDR327Ω+RSENSE–C30.1µFADS1202M0VIN+VIN–M1VDDMCLKMDATGNDC60.1µFSPICLKSPISIMOSPISIMOSPISIMODVDDCLKFIGURE 13. Parallel Operation of ADS1202 in Mode 3.
LAYOUT CONSIDERATIONS
POWER SUPPLIES
The ADS1202 requires only one power supply (VDD). If thereare separate analog and digital power supplies on the board,a good design approach is to have the ADS1202 connectedto the analog power supply. Another approach to control thenoise is the use of a resistor on the power supply. Theconnection can be made between the ADS1202 power-supply pins via a 10Ω resistor. The combination of thisresistor and the decoupling capacitors between the power-supply pins on the ADS1202 provide some filtering. Theanalog supply that is used must be well regulated and lownoise. For designs requiring higher resolution from theADS1202, power-supply rejection will be a concern. Thedigital power supply has high-frequency noise that can becapacitively coupled into the analog portion of the ADS1202.This noise can originate from switching power supplies,microprocessors, or digital signal processors. High-frequencynoise will generally be rejected by the external digital filter atinteger multiples of MCLK. Just below and above thesefrequencies, noise will alias back into the passband of thedigital filter, affecting the conversion result. Inputs to theADS1202, such as VIN+, VIN–, and MCLK should not bepresent before the power supply is on. Violating this condi-tion could cause latch-up. If these signals are present beforethe supply is on, series resistors should be used to limit the
input current. Experimentation may be the best way todetermine the appropriate connection between the ADS1202and different power supplies.
GROUNDING
Analog and digital sections of the design must be carefullyand cleanly partitioned. Each section should have its ownground plane with no overlap between them. Do not join theground planes, but connect the two with a moderate signaltrace underneath the converter. For multiple converters,connect the two ground planes as close as possible to onecentral location for all of the converters. In some cases,experimentation may be required to find the best point toconnect the two planes together.
DECOUPLING
Good decoupling practices must be used for the ADS1202and for all components in the design. All decoupling capaci-tors, specifically the 0.1µF ceramic capacitors, must beplaced as close as possible to the pin being decoupled. A1µF and 10µF capacitor, in parallel with the 0.1µF ceramiccapacitor, must be used to decouple VDD to GND. At leastone 0.1µF ceramic capacitor must be used to decouple VDDto GND, as well as for the digital supply on each digitalcomponent.
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PACKAGE DRAWING
PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153ADS1202
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MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.
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