512K Bits x 32 Bits x 4 Banks (64-MBIT)SYNCHRONOUS DYNAMIC RAM
FEATURES
•Clock frequency: 200, 166, 143 MHz•Fully synchronous; all signals referenced to apositive clock edge•Internal bank for hiding row access/precharge•Single 3.3V power supply•LVTTL interface
•Programmable burst length:(1, 2, 4, 8, full page)•Programmable burst sequence:Sequential/Interleave•Self refresh modes
•4096 refresh cycles every 64 ms
•Random column address every clock cycle•Programmable CAS latency (2, 3 clocks)•Burst read/write and burst read/single writeoperations capability•Burst termination by burst stop and prechargecommand•Available in Industrial temperature grade•Available in 400-mil 86-pin TSOP II and 90-ballBGA•Available in Lead free
•Power Down and Deep Power Down Mode•Partial Array Self Refresh
•Temperature Compensated Self Refresh•Output Driver Strength Selection
Please contact Production Manager for Mobilefunction detail.
ADVANCEDINFORMATION
JUNE 2008
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S32200E is organized
as 524,288 bits x 32-bit x 4-bank for improved performance.The synchronous DRAMs achieve high-speed data transferusing pipeline architecture. All inputs and outputs signalsrefer to the rising edge of the clock input.
KEY TIMING PARAMETERS
ParameterClk Cycle TimeCAS Latency = 3CAS Latency = 2Clk FrequencyCAS Latency = 3 CAS Latency = 2Access Time from ClockCAS Latency = 3CAS Latency = 2-55102001004.57.5-66101661005.57.5-77101431005.58UnitnsnsMhzMhznsnsCopyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
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IS42S32200E
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamicrandom-access memory designed to operate in 3.3Vmemory systems containing 67,108,864 bits. Internallyconfigured as a quad-bank DRAM with a synchronousinterface. Each 16,777,216-bit bank is organized as 2,048rows by 256 columns by 32 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,and a power-saving, power-down mode. All signals areregistered on the positive edge of the clock signal, CLK.All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burstdata at a high data rate with automatic column-addressgeneration, the ability to interleave between internal banksto hide precharge time and the capability to randomlychange column addresses on each clock cycle duringburst access.
A self-timed row precharge initiated at the end of the burstsequence is available with the AUTO PRECHARGE
function enabled.Precharge one bank while accessing oneof the other three banks will hide the precharge cycles andprovide seamless, high-speed, random-access operation.SDRAM read and write accesses are burst oriented startingat a selected location and continuing for a programmednumber of locations in a programmed sequence. Theregistration of an ACTIVE command begins accesses,followed by a READ or WRITE command. The ACTIVEcommand in conjunction with address bits registered areused to select the bank and row to be accessed (BA0, BA1select the bank; A0-A10 select the row). The READ orWRITE commands in conjunction with address bits reg-istered are used to select the starting column location forthe burst access.
Programmable READ or WRITE burst lengths consist of1, 2, 4 and 8 locations or full page, with a burst terminateoption.
FUNCTIONAL BLOCK DIAGRAM
CLKCKECSRASCASWEDQM0-3COMMANDDECODER&CLOCKGENERATORDATA INBUFFER3232MODEREGISTER11REFRESHCONTROLLERDQ 0-31 SELFREFRESHCONTROLLERA10A9A8A7A6A5A4A3A2A1A0BA0BA111DATA OUTBUFFER3232VDD/VDDQGND/GNDQREFRESHCOUNTER2048204820482048ROW DECODERMULTIPLEXERMEMORY CELLARRAY11ROWADDRESSLATCH11ROWADDRESSBUFFERBANK 0SENSE AMP I/O GATECOLUMNADDRESS LATCH256(x 32)BANK CONTROL LOGICBURST COUNTERCOLUMN DECODERCOLUMNADDRESS BUFFER2
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IS42S32200E
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDDQM0WECASRASCSNCBA0BA1A10A0A1A2DQM2VDDNCDQ16VSSQDQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQDQ23VDD12345678910111213141516171819202122232425262728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43868584838281807978777675747372717069686766656463626160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44VSSDQ15VSSQ DQ14 DQ13 VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8 NCVSSDQM1NCNCCLKCKE A9 A8A7 A6A5A4A3DQM3VSSNC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27VDDQ DQ26 DQ25 VSSQ DQ24 VSSPIN DESCRIPTIONS
A0-A10A0-A7BA0, BA1DQ0 to DQ31CLKCKECSRASCAS
Row Address InputColumn Address InputBank Select AddressData I/O
System Clock InputClock EnableChip Select
Row Address Strobe CommandColumn Address Strobe Command
WE
DQM0-DQM3VDDVssVDDQVssQNC
Write Enable
x32 Input/Output MaskPowerGround
Power Supply for I/O PinGround for I/O PinNo Connection
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IS42S32200E
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9ABCDEFGHJKLMNPRPIN DESCRIPTIONS
A0-A10A0-A7BA0, BA1DQ0 to DQ31CLKCKECSRASCAS
Row Address InputColumn Address InputBank Select AddressData I/O
System Clock InputClock EnableChip Select
Row Address Strobe CommandColumn Address Strobe Command
WE
DQM0-DQM3VDDVssVDDQVssQNC
Write Enable
x32 Input/Output MaskPowerGround
Power Supply for I/O PinGround for I/O PinNo Connection
DQ26DQ24VSSVDDDQ23DQ21VDDQVSSQDQ19DQ22DQ20VDDQDQ17DQ18VDDQNCA2A10NCBA0CASVDDDQ6DQ1DQ16VSSQDQM2VDDA0BA1CSA1NCRASDQ28VDDQVSSQVSSQDQ27DQ25VSSQDQ29DQ30VDDQDQ31VSSDQM3A4A7CLKDQM1A5A8CKENCNCA3A6NCA9NCVSSWEDQM0DQ7VSSQDQ5VDDQDQ3VDDQVDDQDQ8VSSQDQ10DQ9VSSQDQ12DQ14DQ11VDDQVSSQDQ13DQ15VSSVDDQVSSQDQ4VDDDQ0DQ24
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IS42S32200E
PIN FUNCTIONS
SymbolA0-A10Pin No. (TSOP)25 to 2760 to 6624TypeInput PinFunction (In Detail)Address Inputs: A0-A10 are sampled during the ACTIVEcommand (row-address A0-A10) and READ/WRITE command (A0-A7with A10 defining auto precharge) to select one location out of the memory arrayin the respective bank. A10 is sampled during a PRECHARGE command todetermine if all banks are to be precharged (A10 HIGH) or bank selected byBA0, BA1 (LOW). The address inputs also provide the op-code during a LOADMODE REGISTER command.Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,WRITE or PRECHARGE command is being applied.CAS, in conjunction with the RAS and WE, forms the device command. See the\"Command Truth Table\" for details on device commands.The CKE input determines whether the CLK input is enabled. The next rising edgeof the CLK signal will be valid when is CKE HIGH and invalid when LOW. WhenCKE is LOW, the device will be in either power-down mode, clock suspend mode,or self refresh mode. CKE is an asynchronous input.CLK is the master clock input for this device. Except for CKE, all inputs to thisdevice are acquired in synchronization with the rising edge of this pin.The CS input determines whether command input is enabled within the device.Command input is enabled when CS is LOW, and disabled with CS is HIGH. Thedevice remains in the previous state when CS is HIGH.DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte unitsusing the DQM0-DQM3 pinsBA0, BA1CASCKE22,231867Input PinInput PinInput PinCLKCS6820Input PinInput PinDQ0 to2, 4, 5, 7, 8, 10,11,13DQ3174,76,77,79,80,82,83,8545,47,48,50,51,53,54,5631,33,34,36,37,39,40,42 DQM0DQM316,28,59,71DQ PinInput PinDQMx control thel ower and upper bytes of the DQ buffers. In read mode,the output buffers are place in a High-Z state. During a WRITE cycle the input data ismasked. When DQMx is sampled HIGH and is an input mask signal for write accessesand an output enable signal for read accesses. DQ0 through DQ7 are controlled byDQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through DQ23 arecontrolled by DQM2. DQ24 through DQ31 are controlled by DQM3.RAS, in conjunction with CAS and WE, forms the device command. See the \"CommandTruth Table\" item for details on device commands.WE, in conjunction with RAS and CAS, forms the device command. See the \"CommandTruth Table\" item for details on device commands.VDDQ is the output buffer power supply.VDD is the device internal power supply.GNDQ is the output buffer ground.GND is the device internal ground.RASWEVDDQVDDGNDQGND19173,9,35,41,49,55,75,811,15,29,436,12,32,38,46,52,78,8444,58,72,86Input Pin Input PinSupply PinSupply PinSupply PinSupply PinIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.00D06/02/08
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IS42S32200E
FUNCTION (In Detail)
A0-A10 are address inputs sampled during the ACTIVE(row-address A0-A10) and READ/WRITE command (A0-A7with A10 defining auto PRECHARGE). A10 is sampled duringa PRECHARGE command to determine if all banks are tobe PRECHARGED (A10 HIGH) or bank selected by BA0,BA1 (LOW). The address inputs also provide the op-codeduring a LOAD MODE REGISTER command.
Bank Select Address (BA0 and BA1) defines which bank theACTIVE, READ, WRITE or PRECHARGE command isbeing applied.
CAS, in conjunction with the RAS and WE, forms thedevice command. See the “Command Truth Table” fordetails on device commands.
The CKE input determines whether the CLK input isenabled. The next rising edge of the CLK signal will bevalid when is CKE HIGH and invalid when LOW. WhenCKE is LOW, the device will be in either power-downmode, CLOCK SUSPEND mode, or SELF-REFRESHmode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except forCKE, all inputs to this device are acquired in synchroni-zation with the rising edge of this pin.
The CS input determines whether command input isenabled within the device. Command input is enabledwhen CS is LOW, and disabled with CS is HIGH. Thedevice remains in the previous state when CS is HIGH. DQ0through DQ7 are controlled by DQM0. DQ8 through DQ15are controlled by DQM1. DQ16 through DQ23 are controlledby DQM2. DQ24 through DQ31 are controlled by DQM3. Inread mode, DQMx control the output buffer. When DQMx isLOW, the corresponding buffer byte is enabled, and whenHIGH, disabled. The outputs go to the HIGH ImpedanceState when DQMx is HIGH. This function corresponds toOE in conventional DRAMs. In write mode, DQMx controlthe input buffer. When DQMx is LOW, the correspondingbuffer byte is enabled, and data can be written to the device.When DQMx is HIGH, input data is masked and cannot bewritten to the device.
RAS, in conjunction with CAS and WE , forms the devicecommand. See the “Command Truth Table” item fordetails on device commands.
WE , in conjunction with RAS and CAS , forms the devicecommand. See the “Command Truth Table” item fordetails on device commands.
VDDQ is the output buffer power supply.VDD is the device internal power supply.GNDQ is the output buffer ground.GND is the device internal ground.
READ
The READ command selects the bank from BA0, BA1inputs and starts a burst read access to an active row.Inputs A0-A7 provides the starting column location. WhenA10 is HIGH, this command functions as an AUTOPRECHARGE command. When the auto precharge isselected, the row being accessed will be precharged atthe end of the READ burst. The row will remain open forsubsequent accesses when AUTO PRECHARGE is notselected. DQ’s read data is subject to the logic level onthe DQM inputs two clocks earlier. When a given DQMsignal was registered HIGH, the corresponding DQ’s willbe High-Z two clocks later. DQ’s will provide valid datawhen the DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with theWRITE command. BA0, BA1 inputs selects the bank, andthe starting column location is provided by inputs A0-A7.Whether or not AUTO-PRECHARGE is used is deter-mined by A10.
The row being accessed will be precharged at the end ofthe WRITE burst, if AUTO PRECHARGE is selected. IfAUTO PRECHARGE is not selected, the row will remainopen for subsequent accesses.
A memory array is written with corresponding input dataon DQ’s and DQM input logic level appearing at the sametime. Data will be written to memory when DQM signal isLOW. When DQM is HIGH, the corresponding data inputswill be ignored, and a WRITE will not be executed to thatbyte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate theopen row in a particular bank or the open row in all banks.BA0, BA1 can be used to select which bank is prechargedor they are treated as “Don’t Care”. A10 determinedwhether one or all banks are precharged. After executingthis command, the next command for the selected banks(s)is executed after passage of the period tRP, which is theperiod required for bank precharging. Once a bank hasbeen precharged, it is in the idle state and must beactivated prior to any READ or WRITE commands beingissued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that theprecharge is initiated at the earliest valid stage within aburst. This function allows for individual-bank prechargewithout requiring an explicit command. A10 to enables theAUTO PRECHARGE function in conjunction with a spe-cific READ or WRITE command. For each individualREAD or WRITE command, auto precharge is either
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IS42S32200E
enabled or disabled. AUTO PRECHARGE does not applyexcept in full-page burst mode. Upon completion of theREAD or WRITE burst, a precharge of the bank/row thatis addressed is automatically performed.
BURST TERMINATE
The BURST TERMINATE command forcibly terminatesthe burst read and write operations by truncating eitherfixed-length or full-page bursts and the most recentlyregistered READ or WRITE command prior to the BURSTTERMINATE.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.The row address and bank to be refreshed are automaticallygenerated during this operation.The stipulated period (tRC)is required for a single refresh operation, and no othercommands can be executed during this period.This com-mand is executed at least 4096 times every 64ms. Duringan AUTO REFRESH command, address bits are “Don’tCare”. This command corresponds to CBR Auto-refresh.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from beingexecuted. Operations in progress are not affected, apartfrom whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwantedcommands from being registered during idle or waitstates.
SELF REFRESH
During the SELF REFRESH operation, the row address tobe refreshed, the bank, and the refresh interval aregenerated automatically internally. SELF REFRESH canbe used to retain data in the SDRAM without externalclocking, even if the rest of the system is powered down.The SELF REFRESH operation is started by dropping theCKE pin from HIGH to LOW. During the SELF REFRESHoperation all other inputs to the SDRAM become “Don’tCare”.The device must remain in self refresh mode for aminimum period equal to tRAS or may remain in self refreshmode for an indefinite period beyond that.The SELF-REFRESH operation continues as long as the CKE pinremains LOW and there is no need for external control ofany other pins.The next command cannot be executeduntil the device internal recovery period (tRC) has elapsed.Once CKE goes HIGH, the NOP command must beissued (minimum of two clocks) to provide time for thecompletion of any internal refresh in progress. After theself-refresh, since it is impossible to determine the ad-dress of the last row to be refreshed, an AUTO-REFRESHshould immediately be performed for all addresses.
LOAD MODE REGISTER
During the LOAD MODE REGSITER command the moderegister is loaded from A0-A10. This command can onlybe issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1inputs selects a bank to be accessed, and the addressinputs on A0-A10 selects the row. Until a PRECHARGEcommand is issued to the bank, the row remains open foraccesses.
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IS42S32200E
TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION
COMMAND INHIBIT (NOP)NO OPERATION (NOP)
ACTIVE (Select bank and activate row)(3)READ (Select bank/column, start READ burst)BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)AUTO REFRESH or SELF REFRESH(Enter self refresh mode)LOAD MODE REGISTER
(2)(8)(6,7)(5)(4)(4)CSHLLLLLLLL——
RASXHLHHHLLL——
CASXHHLLHHLL——
WEXHHHLLLHL——
DQMXXXL/H(8)L/H(8)XXXXLH
ADDRXXBank/RowBank/ColBank/Col
XCodeXOp-Code——
DQsXXXXValidActiveXXXActiveHigh-Z
WRITE (Select bank/column, start WRITE burst)Write Enable/Output EnableWrite Inhibit/Output High-Z
(8)NOTES:
1.CKE is HIGH for all commands except SELF REFRESH.2.A0-A10 define the op-code written to the mode register.
3.A0-A10 provide row address, and BA0, BA1 determine which bank is made active.
4.A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disablesauto precharge; BA0, BA1 determine which bank is being read from or written to.
5.A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”6.AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7.Internal refresh counter controls row addressing; all inputs and DQs are “Don’t Care” except for CKE.8.Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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IS42S32200E
TRUTH TABLE – CKE (1-4)
CURRENT STATEPower-DownSelf RefreshClock SuspendPower-DownSelf Refresh
(5)(6)(7)COMMANDnXXX
COMMAND INHIBIT or NOPCOMMAND INHIBIT or NOPX
COMMAND INHIBIT or NOPAUTO REFRESHVALID
ACTIONn
Maintain Power-DownMaintain Self RefreshMaintain Clock SuspendExit Power-DownExit Self RefreshExit Clock SuspendPower-Down EntrySelf Refresh EntryClock Suspend Entry
CKEn-1
LLLLLLHHHH
CKEnLLLHHHLLLH
Clock SuspendAll Banks IdleAll Banks Idle
Reading or Writing
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK nNOTES:
1.CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.2.Current state is the state of the SDRAM immediately prior to clock edge n.
3.COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn.4.All states and sequences not shown are illegal or reserved.
5.Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tCKS is met).6.Exiting self refresh at clock edge n will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commandsshould be issued on clock edges occurring during the tXSR period. A minimum of two NOP commands must be sent during tXSR period.7.After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENT STATEAnyIdle
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)NO OPERATION (NOP/Continue previous operation)ACTIVE (Select and activate row) AUTO REFRESH(7)
LOAD MODE REGISTER(7)PRECHARGE(11)
Row Active
READ (Select column and start READ burst)(10)WRITE (Select column and start WRITE burst)(10)PRECHARGE (Deactivate row in bank or banks)(8)
Read(AutoPrechargeDisabled)Write(AutoPrechargeDisabled)
READ (Select column and start new READ burst)(10)WRITE (Select column and start WRITE burst)(10)
PRECHARGE (Truncate READ burst, start PRECHARGE)(8)BURST TERMINATE(9)
READ (Select column and start READ burst)(10)
WRITE (Select column and start new WRITE burst)(10)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8)BURST TERMINATE(9)
CSRASCASWEHLLLLLLLLLLLLLLLL
XHLLLLHHLHHLHHHLH
XHHLLHLLHLLHHLLHH
XHHHLLHLLHLLLHLLL9
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IS42S32200E
NOTE:
1.This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after tXSR has been met (if theprevious state was SELF REFRESH).
2.This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are thoseallowed to be issued to that bank when in that state. Exceptions are covered in the notes below.3.Current state definitions:
Idle:The bank has been precharged, and tRP has been met.
Row Active:A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4.The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, orallowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands tothe other bank are determined by its current state and CURRENT STATE BANK n truth tables.
Precharging:Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank
will be in the idle state.
Row Activating:Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will
be in the row active state.
Read w/Auto
Precharge Enabled:Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met.
Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled:Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met.
Once tRP is met, the bank will be in the idle state.
5.The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must beapplied on each positive clock edge during these states.
Refreshing:Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the
SDRAM will be in the all banks idle state.
Accessing ModeRegister:Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once
tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All:Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all
banks will be in the idle state.
6.All states and sequences not shown are illegal or reserved.7.Not bank-specific; requires that all banks are idle.
8.May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.9.Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10.READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs
or WRITEs with auto precharge disabled.
11.Does not affect the state of the bank and acts as a NOP to that bank.
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分销商库存信息:
ISSI
IS42S32200E-7TLIS42S32200E-7BLIIS42S32200E-7TLI-TRIS42S32200E-6TLI-TRIS42S32200E-6TLIIS42S32200E-6B-TRIS42S32200E-6BI-TR
IS42S32200E-6TLIS42S32200E-7TL-TRIS42S32200E-7BL-TRIS42S32200E-7BLIS42S32200E-6BLIS42S32200E-6BLIIS42S32200E-6BI
IS42S32200E-7TLIIS42S32200E-6TL-TRIS42S32200E-6BL-TRIS42S32200E-7BLI-TRIS42S32200E-6BLI-TRIS42S32200E-6B
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