Dual-phase delay-locked loop circuit and method

专利名称：Dual-phase delay-locked loop circuit and

method

发明人：Adrian J. Drexler申请号：US09974386申请日：20011009

公开号：US20030067331A1公开日：20030410

专利附图：

摘要：A delay-locked loop includes a clock multiplier that generates a multipliedclock signal responsive to an input clock signal. The multiplied clock signal has afrequency that is a multiple of a frequency of the input clock signal. A variable delay

circuit generates a delayed clock signal responsive to the multiplied clock signal, thedelayed clock signal having a delay relative to the multiplied clock signal. The variabledelay circuit controls the value of the delay responsive to a delay control signal. Acomparison circuit generates the delay control signal in response to the relative phasesof the delayed clock signal and the multiplied clock signal. In another embodiment, thedelay-locked loop omits the clock multiplier and instead includes a comparison circuitthat generates the delay control signal in response to the relative phases of both therising- and falling-edge transitions of the delayed and input clock signals.

申请人：DREXLER ADRIAN J.

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