24C02C-EP资料

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MFEATURES24C02C2K 5.0V I2C™ Serial EEPROMPACKAGE TYPESPDIP/SOICA0A1A2Vss18VccWPSCLSDA•Single supply with operation from 4.5 to 5.5V•Low power CMOS technology-1 mA active current typical

-10 µA standby current typical at 5.5V

•Organized as a single block of 256 bytes (256 x 8)•Hardware write protection for upper half of array•2-wire serial interface bus, I2C compatible•100 kHz and 400 kHz compatibility•Page-write buffer for up to 16 bytes

•Self-timed write cycle (including auto-erase)

•Fast 1 mS write cycle time for byte or page mode•Address lines allow up to eight devices on bus•1,000,000 erase/write cycles guaranteed•ESD protection > 4,000V•Data retention > 200 years

•8-pin PDIP, SOIC or TSSOP packages•Available for extended temperature ranges-Commercial (C):0°Cto+70°C-Industrial (I): -40°Cto+85°C-Automotive (E): -40°Cto+125°C

24C02C234765TSSOPA0A1A2VSS12348765VCCWPSCLSDA24C02CDESCRIPTION

The Microchip Technology Inc. 24C02C is a 2K bitSerial Electrically Erasable PROM with a voltage rangeof 4.5V to 5.5V. The device is organized as a singleblock of 256 x 8-bit memory with a 2-wire serial inter-face. Low current design permits operation with typicalstandby and active currents of only 10 µA and 1 mArespectively. The device has a page-write capability forup to 16 bytes of data and has fast write cycle times ofonly 1 mS for both byte and page writes. Functionaladdress lines allow the connection of up to eight24C02C devices on the same bus for up to 16K bits ofcontiguous EEPROM memory. The device is availablein the standard 8-pin PDIP, 8-pin SOIC (150 mil), andTSSOP packages.

BLOCK DIAGRAMA0 A1 A2WPHV Generator I/OControl LogicMemoryControl LogicXDECEEPROM ArraySDASCLVccVssWrite Protect CircuitryYDECSENSE AMPR/W CONTROLI2C is a trademark of Philips Corporation.© 1997 Microchip Technology Inc.PreliminaryDS21202A-page 1元器件交易网www.cecb2b.com

24C02C

1.0

1.1

ELECTRICAL

CHARACTERISTICS

Maximum Ratings*TABLE 1-1:

NameVSSSDASCLVCCA0, A1, A2

PIN FUNCTION TABLE

FunctionGroundSerial Data Serial Clock

+4.5V to 5.5V Power SupplyChip Selects

Hardware Write Protect

VCC........................................................................7.0VAll inputs and outputs w.r.t. VSS......-0.6V to VCC +1.0VStorage temperature...........................-65˚C to +150˚CAmbient temp. with power applied.......-65˚C to +125˚CSoldering temperature of leads (10 seconds)...+300˚CESD protection on all pins......................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings” maycause permanent damage to the device. This is a stress rating only andfunctional operation of the device at those or any other conditionsabove those indicated in the operational listings of this speciﬁcation isnot implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.

TABLE 1-2:DC CHARACTERISTICS

VCC = +4.5V to +5.5VCommercial (C):Industrial (I):Automotive (E):SymbolVIHVILVHYSVOLILIILOCIN, COUTICC ReadICC WriteICCS

Min.0.7 VCC

—0.05 VCC

—-10-10————

Tamb = 0°C to +70°CTamb = -40°C to +85°CTamb = -40°C to +125°CMax.—0.3 VCC

—0.401010101350

UnitsVVVVµAµApFmAmAµA

(Note)

IOL = 3.0 mA, Vcc = 4.5VVIN = 0.1V to 5.5V, WP = VssVOUT = 0.1V to 5.5VVCC = 5.0V (Note)

Tamb = 25°C, f = 1 MHzVCC = 5.5V, SCL = 400 kHzVCC = 5.5V

VCC = 5.5V, SDA = SCL = VCC

Conditions

All parameters apply across the speci-ﬁed operating ranges unless otherwise noted.

Parameter

SCL and SDA pins:

High level input voltage

Low level input voltage

Hysteresis of Schmitt trigger inputsLow level output voltageInput leakage currentOutput leakage current

Pin capacitance (all inputs/outputs)Operating currentStandby current

Note: This parameter is periodically sampled and not 100% tested.

24C02C

TABLE 1-3:AC CHARACTERISTICS

Vcc = 4.5V to 5.5VCommercial (C):Industrial (I):Automotive (E):Max.100——1000300—————3500—

Min.—6001300——6006000100600—1300

Tamb = 0°C to +70°CTamb = -40°C to +85°CTamb = -40°C to +125°CMax.400——300300—————900—

UnitskHznsnsnsnsnsnsnsnsnsnsns

Remarks

All parameters apply across the speciﬁed oper-ating ranges unless otherwise noted.

Parameter

Clock frequencyClock high timeClock low time

SDA and SCL rise timeSDA and SCL fall timeSTART condition hold timeSTART condition setup timeData input hold timeData input setup time

STOP condition setup timeOutput valid from clockBus free time

SymbolFCLKTHIGHTLOWTRTFTHD:STATSU:STATHD:DATTSU:DATTSU:STOTAATBUF

Tamb > +85°CMin.—40004700——4000470002504000—4700

-40°C ≤ Tamb ≤ +85°C

(Note 1)(Note 1)

After this period the ﬁrst clock pulse is generatedOnly relevant for repeated START condition(Note 2)

Output fall time from VIHminimum to VIL maximumInput ﬁlter spike suppression(SDA and SCL pins)Write cycle timeEndurance

TOFTSPTWR

———1M

250501.5—

20 + 0.1 CB

——1M

250501—

nsns

(Note 2)

Time the bus must be free before a new transmission can start

(Note 1), CB ≤ 100 pF(Note 3)

msByte or Page mode

cycles25°C, VCC = 5.0V, Block

Mode (Note 4)

Note 1:Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined TSP and VHYS speciﬁcations are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

24C02C

2.0

2.1

PIN DESCRIPTIONS

SDA Serial Data3.0FUNCTIONAL DESCRIPTION

This is a bi-directional pin used to transfer addressesand data into and data out of the device. It is an opendrain terminal, therefore the SDA bus requires a pull-upresistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for400 kHz).

For normal data transfer SDA is allowed to change onlyduring SCL low. Changes during SCL high are reservedfor indicating the START and STOP conditions.

The 24C02C supports a bi-directional 2-wire bus anddata transmission protocol. A device that sends dataonto the bus is deﬁned as transmitter, and a devicereceiving data as receiver. The bus has to be controlledby a master device which generates the serial clock(SCL), controls the bus access, and generates theSTART and STOP conditions, while the 24C02C worksas slave. Both master and slave can operate as trans-mitter or receiver but the master device determineswhich mode is activated.

2.2SCL Serial Clock This input is used to synchronize the data transfer fromand to the device.

2.3A0, A1, A2The levels on these inputs are compared with the cor-responding bits in the slave address. The chip isselected if the compare is true.

Up to eight 24C02C devices may be connected to thesame bus by using different chip select bit combina-tions. These inputs must be connected to either VCC orVSS.

2.4WPThis is the hardware write protect pin. It must be tied toVCC or VSS. If tied to Vcc, the hardware write protectionis enabled. If the WP pin is tied to Vss the hardwarewrite protection is disabled.

2.5Noise ProtectionThe 24C02C employs a VCC threshold detector circuitwhich disables the internal erase/write logic if the VCCis below 3.8 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁltercircuits which suppress noise spikes to assure properdevice operation even on a noisy bus.

24C02C

The data on the line must be changed during the LOWperiod of the clock signal. There is one bit of data perclock pulse.

Each data transfer is initiated with a START conditionand terminated with a STOP condition. The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited, although only the last six-teen will be stored when doing a write operation. Whenan overwrite does occur it will replace data in a ﬁrst inﬁrst out fashion.

4.0BUS CHARACTERISTICS

The following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have beendeﬁned (Figure 4-1).

4.1Bus not Busy (A)4.5AcknowledgeBoth data and clock lines remain HIGH.

4.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while theclock (SCL) is HIGH determines a START condition. Allcommands must be preceded by a START condition.

Each receiving device, when addressed, is required togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this acknowledge bit.Note:The 24C02C does not generate anyacknowledge bits if an internal program-ming cycle is in progress.4.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while theclock (SCL) is HIGH determines a STOP condition. Alloperations must be ended with a STOP condition.

4.4Data Valid (D)The state of the data line represents valid data when,after a START condition, the data line is stable for theduration of the HIGH period of the clock signal.

The device that acknowledges has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGHperiod of the acknowledge related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. A master must signal an end of data to theslave by not generating an acknowledge bit on the lastbyte that has been clocked out of the slave. In this case,the slave must leave the data line HIGH to enable themaster to generate the STOP condition (Figure 4-2).

FIGURE 4-1:SCL(A)(B)DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS(C)(D)(C)(A)SDASTARTCONDITIONADDRESS ORACKNOWLEDGEVALIDDATAALLOWEDTO CHANGESTOPCONDITIONFIGURE 4-2:ACKNOWLEDGE TIMINGAcknowledgeBitSCL1234567123SDAData from transmitterTransmitter must release the SDA line at this pointallowing the Receiver to pull the SDA line low toacknowledge the previous eight bits of data.Data from transmitterReceiver must release the SDA line at this pointso the Transmitter can continue sending data.© 1997 Microchip Technology Inc.PreliminaryDS21202A-page 5元器件交易网www.cecb2b.com

24C02C

5.0

DEVICE ADDRESSING

FIGURE 5-1:CONTROL BYTE FORMAT Read/Write BitChip SelectBits0A2A1A0R/WACKA control byte is the ﬁrst byte received following thestart condition from the master device (Figure 5-1). Thecontrol byte consists of a four bit control code; for the24C02C this is set as 1010 binary for read and writeoperations. The next three bits of the control byte arethe chip select bits (A2, A1, A0). The chip select bitsallow the use of up to eight 24C02C devices on thesame bus and are used to select which device isaccessed. The chip select bits in the control byte mustcorrespond to the logic levels on the corresponding A2,A1, and A0 pins for the device to respond. These bitsare in effect the three most signiﬁcant bits of the wordaddress.

The last bit of the control byte deﬁnes the operation tobe performed. When set to a one a read operation isselected, and when set to a zero a write operation isselected. Following the start condition, the 24C02Cmonitors the SDA bus checking the control byte beingtransmitted. Upon receiving a 1010 code and appropri-ate chip select bits, the slave device outputs anacknowledge signal on the SDA line. Depending on thestate of the R/W bit, the 24C02C will select a read orwrite operation.

Control CodeS101Slave AddressStart BitAcknowledge Bit5.1

Contiguous Addressing Across Multiple DevicesThe chip select bits A2, A1, A0 can be used to expandthe contiguous address space for up to 16K bits by add-ing up to eight 24C02C devices on the same bus. In thiscase, software can use A0 of the control byte asaddress bit A8, A1 as address bit A9, and A2 asaddress bit A10. It is not possible to write or read acrossdevice boundaries.

24C02C

6.2

Page WriteThe write control byte, word address and the ﬁrst databyte are transmitted to the 24C02C in the same way asin a byte write. But instead of generating a stop condi-tion, the master transmits up to 15 additional data bytesto the 24C02C which are temporarily stored in the on-chip page buffer and will be written into the memoryafter the master has transmitted a stop condition. Afterthe receipt of each word, the four lower order addresspointer bits are internally incremented by one. Thehigher order four bits of the word address remains con-stant. If the master should transmit more than 16 bytesprior to generating the stop condition, the addresscounter will roll over and the previously received datawill be overwritten. As with the byte write operation,once the stop condition is received an internal writecycle will begin (Figure 6-2). If an attempt is made towrite to the protected portion of the array when thehardware write protection has been enabled, the devicewill acknowledge the command but no data will be writ-ten. The write cycle time must be observed even if thewrite protection is enabled.

6.0

6.1

WRITE OPERATIONS

Byte WriteFollowing the start signal from the master, the devicecode(4 bits), the chip select bits (3 bits), and the R/Wbit which is a logic low is placed onto the bus by themaster transmitter. The device will acknowledge thiscontrol byte during the ninth clock pulse. The next bytetransmitted by the master is the word address and willbe written into the address pointer of the 24C02C. Afterreceiving another acknowledge signal from the24C02C the master device will transmit the data wordto be written into the addressed memory location. The24C02C acknowledges again and the master gener-ates a stop condition. This initiates the internal writecycle, and during this time the 24C02C will not generateacknowledge signals (Figure 6-1). If an attempt is madeto write to the protected portion of the array when thehardware write protection has been enabled, the devicewill acknowledge the command but no data will be writ-ten. The write cycle time must be observed even if thewrite protection is enabled.

6.3WRITE PROTECTIONThe WP pin must be tied to VCC or VSS. If tied to VCC,the upper half of the array (080-0FF) will be write pro-tected. If the WP pin is tied to VSS, then write operationsto all address locations are allowed.

FIGURE 6-1:BUS ACTIVITYMASTERSDA LINEBYTE WRITESTARTSACKACKACKCONTROLBYTEWORDADDRESSDATASTOPPBUS ACTIVITYFIGURE 6-2:BUS ACTIVITYMASTERPAGE WRITESTARTCONTROLBYTEWORDADDRESS (n)STOPDATA nDATA n +1DATA n + 15SDA LINEBUS ACTIVITYSACKACKACKACKACKP© 1997 Microchip Technology Inc.PreliminaryDS21202A-page 7元器件交易网www.cecb2b.com

24C02C

7.0

ACKNOWLEDGE POLLING

FIGURE 7-1:

Since the device will not acknowledge during a writecycle, this can be used to determine when the cycle iscomplete (this feature can be used to maximize busthroughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling canbe initiated immediately. This involves the master send-ing a start condition followed by the control byte for awrite command (R/W = 0). If the device is still busy withthe write cycle, then no ACK will be returned. If no ACKis returned, then the start bit and control byte must bere-sent. If the cycle is complete, then the device willreturn the ACK and the master can then proceed withthe next read or write command. See Figure 7-1 for ﬂowdiagram.

ACKNOWLEDGE POLLING FLOWSendWrite CommandSend StopCondition toInitiate Write CycleSend StartSend Control Bytewith R/W = 0Did DeviceAcknowledge(ACK = 0)?YESNextOperationNODS21202A-page 8Preliminary© 1997 Microchip Technology Inc.元器件交易网www.cecb2b.com

24C02C

address is sent, the master generates a start conditionfollowing the acknowledge. This terminates the writeoperation, but not before the internal address pointer isset. Then the master issues the control byte again butwith the R/W bit set to a one. The 24C02C will thenissue an acknowledge and transmits the eight bit dataword. The master will not acknowledge the transfer butdoes generate a stop condition and the 24C02C dis-continues transmission (Figure 8-2). After this com-mand, the internal address counter will point to theaddress location following the one that was just read.

8.0READ OPERATIONS

Read operations are initiated in the same way as writeoperations with the exception that the R/W bit of theslave address is set to one. There are three basic typesof read operations: current address read, random read,and sequential read.

8.1Current Address ReadThe 24C02C contains an address counter that main-tains the address of the last word accessed, internallyincremented by one. Therefore, if the previous readaccess was to address n, the next current address readoperation would access data from address n + 1. Uponreceipt of the slave address with the R/W bit set to one,the 24C02C issues an acknowledge and transmits theeight bit data word. The master will not acknowledgethe transfer but does generate a stop condition and the24C02C discontinues transmission (Figure 8-1).

8.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24C02C transmits theﬁrst data byte, the master issues an acknowledge asopposed to a stop condition in a random read. Thisdirects the 24C02C to transmit the next sequentiallyaddressed 8-bit word (Figure 8-3).

To provide sequential reads the 24C02C contains aninternal address pointer which is incremented by one atthe completion of each operation. This address pointerallows the entire memory contents to be serially readduring one operation. The internal address pointer willautomatically roll over from address FF to address 00.

8.2Random ReadRandom read operations allow the master to accessany memory location in a random manner. To performthis type of read operation, ﬁrst the word address mustbe set. This is done by sending the word address to the24C02C as part of a write operation. After the word

FIGURE 8-1:CURRENT ADDRESS READBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTARTCONTROLBYTESTOPSACKDATANOACKPFIGURE 8-2:RANDOM READSTARTCONTROLBYTEWORDADDRESS (n)STARTCONTROLBYTESTOPBUS ACTIVITYMASTERSDA LINESACKACKSACKDATA (n)NO ACKPBUS ACTIVITYFIGURE 8-3:SEQUENTIAL READCONTROLBYTEDATA nDATA n + 1DATA n + 2DATA n + XBUS ACTIVITY MASTERSDA LINEBUS ACTIVITYSTOPPNOACKACKACKACKACK© 1997 Microchip Technology Inc.PreliminaryDS21202A-page 9元器件交易网www.cecb2b.com

24C02C

NOTES:

24C02C

24C02C PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.24C02C—/PPackage:Temperature Range:Device:P=Plastic DIP (300 mil Body), 8-leadSN=Plastic SOIC, (150 mil Body), 8-leadST=TSSOP (4.4 mm Body), 8-leadBlank=0°C to +70°CI=–40°C to +85°CE=–40°C to +125°C24C02C24C02CT2K I2C Serial EEPROM2K I2C Serial EEPROM (Tape and Reel)Sales and SupportData Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Your local Microchip sales ofﬁce (see last page).

2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.

3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

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Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation orwarranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or otherintellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with expresswritten approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarksof Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.DS21202A-page 12Preliminary© 1997 Microchip Technology Inc.

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